Charlie Hwang

A 45nm SOI embedded DRAM macro for POWER7TM 32MB on-chip L3 cache

Erik Nelson, Donald W. Plass, Gregory Fredeman, 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

A 90 nm 16 Mb embedded phase-change memory macro with write current smoothing and enhanced write bandwidth

Qin Li, Zheng Li, Ruizhe Wang, 2011, 2011 9th IEEE International Conference on ASIC.

A 45 nm SOI Embedded DRAM Macro for the POWER™ Processor 32 MByte On-Chip L3 Cache

Erik Nelson, Toshiaki Kirihata, Donald W. Plass, 2011, IEEE Journal of Solid-State Circuits.

Power-constrained high-frequency circuits for the IBM POWER6 microprocessor

Yiu-Hing Chan, Leon J. Sigal, Joshua Friedrich, 2007, IBM J. Res. Dev..