Takashi Ipposhi

发表

Ultra-high-speed and low-power SOI CMOS technology with body-tied hybrid trench isolation structure

Y. Ohji, M. Inuishi, Yuuichi Hirano, 2004 .

Investigation into HCl improvement by a split-reeessed-gate structure in an STI-based nLDMOSFET

Takahiro Mori, Hiroki Fujii, Takashi Ipposhi, 2017, 2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD).

Suppression of delay time instability on frequency using field shield isolation technology for deep sub-micron SOI circuits

Koichiro Mashiko, K. Ueda, Y. Inoue, 1996, International Electron Devices Meeting. Technical Digest.

Impact of 0.18 /spl mu/m SOI CMOS technology using hybrid trench isolation with high resistivity substrate on embedded RF/analog applications

T. Iwamatsu, Koichiro Mashiko, Masahide Inuishi, 2000, 2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104).

A Low-Power Microcontroller with Body-Tied SOI Technology

Takahiko Arakawa, Yasunobu Nakase, Yuichi Hirano, 2004 .

Bulk-layout-compatible 0.18 /spl mu/m SOI-CMOS technology using body-fixed partial trench isolation (PTI)

T. Iwamatsu, Masahide Inuishi, Shigeto Maegawa, 1999, 1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345).

A 90nm bulk BiCDMOS platform technology with 15–80V LD-MOSFETs for automotive applications

Takuya Maruyama, Takahiro Mori, Takahiro Maruyama, 2017, 2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD).

Impact of 0.10 /spl mu/m SOI CMOS with body-tied hybrid trench isolation structure to break through the scaling crisis of silicon technology

T. Iwamatsu, Masahide Inuishi, Shigeto Maegawa, 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

An advanced 0.5 /spl mu/m CMOS/SOI technology for practical ultrahigh-speed and low-power circuits

Tsutomu Hirao, Koichiro Mashiko, Takashi Iwamatsu, 1995, 1995 IEEE International SOI Conference Proceedings.

A 0.4 μm Gate-All-Around TFT (GAT) Using a Dummy Nitride Pattern for High-Density Memories

Shigenobu Maeda, Shigeto Maegawa, Natsuro Tsubouchi, 1995 .

A Highly Reliable 0.18 μm SOI CMOS Technology for 3.3V/1.8V Operation Using Hybrid Trench Isolation and Dual Gate Oxide

K. Shiga, M. Inuishi, Shigenobu Maeda, 2001 .

Novel SOI wafer engineering using low stress and high mobility CMOSFET with <100>-channel for embedded RF/analog applications

Shigenobu Maeda, Toshiaki Iwamatsu, Shigeto Maegawa, 2002, Digest. International Electron Devices Meeting,.

An artificial fingerprint device (AFD): a study of identification number applications utilizing characteristics variation of polycrystalline silicon TFTs

Masahide Inuishi, Shigeto Maegawa, Yasuo Inoue, 2003 .

Feasibility of 0.18 /spl mu/m SOI CMOS technology using hybrid trench isolation with high resistivity substrate for embedded RF/analog applications

T. Iwamatsu, Koichiro Mashiko, Masahide Inuishi, 2001 .

SOI Type Pressure Sensor for High Temperature Pressure Measurement

Mikio Bessho, Takashi Ipposhi, Yuji Hase, 1994 .

Wide-Range Threshold Voltage Controllable Silicon on Thin Buried Oxide Integrated with Bulk Complementary Metal Oxide Semiconductor Featuring Fully Silicided NiSi Gate Electrode

Nobuyuki Sugii, Toshiro Hiramoto, Toshiaki Iwamatsu, 2008 .