J. B. Kuo

Parasitic BJT versus DIBL: Floating-body-related subthreshold characteristics of SOI NMOS device

Y. J. Chen, D. Chen, D. H. Lung, 2014, 2014 International Symposium on Integrated Circuits (ISIC).

Gate-Level Dual-Threshold Static Power Optimization Methodology (GDSPOM) Using Path-Based Static Timing Analysis (STA) Technique

J. B. Kuo, B. Chung, J. Kuo, 2006, PATMOS.

Gate tunneling leakage current behavior of 40 nm PD SOI NMOS device considering the floating body effect

Chih-Sheng Yeh, D. Chen, J. B. Kuo, 2010, Microelectron. Reliab..

A novel 0.7 V two-port 6T SRAM memory cell structure with single-bit-line simultaneous read-and-write access (SBLSRWA) capability using partially-depleted SOI CMOS dynamic-threshold technique

J. B. Kuo, S. C. Liu, 1999, 1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345).

0.8 V CMOS content-addressable-memory (CAM) cell circuit with a fast tag-compare capability using bulk PMOS dynamic-threshold (BP-DTMOS) technique based on standard CMOS technology for low-voltage VLSI systems

J. B. Kuo, E. Shen, 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

Gate-level dual-threshold static power optimization methodology (GDSPOM) for designing high-speed low-power SOC applications using 90nm MTCMOS technology

J. B. Kuo, B. Chung, 2006, 2006 IEEE International Symposium on Circuits and Systems.

Energy-efficient CMOS large-load driver circuit with the complementary adiabatic/bootstrap (CAB) technique for low-power TFT-LCD system applications

J. B. Kuo, N. C. Wang, G. Y. Liu, 2005, 2005 IEEE International Symposium on Circuits and Systems.

Gate-level dual-threshold static power optimization methodology (GDSPOM) using path-based static timing analysis (STA) technique for SOC application

J. B. Kuo, B. Chung, 2008, Integr..

MTCMOS low-power optimization technique (LPOT) for 1V pipelined RISC CPU circuit

Young Sik Hong, J. B. Kuo, C. B. Hsu, 2014, 2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS).

MTCMOS low-power design technique (LPDT) for low-voltage pipelined microprocessor circuits

J. B. Kuo, C. B. Hsu, 2014, 2014 International Symposium on Integrated Circuits (ISIC).