Raghuram S. Tupuri

Hierarchical test generation for systems on a chip

Daniel G. Saab, Jacob A. Abraham, Raghuram S. Tupuri, 2000, VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design.

Delay Constrained Register Transfer Level Dynamic Power Estimation

Jacob A. Abraham, Raghuram S. Tupuri, Sriram Sambamurthy, 2006, PATMOS.

Design Migration Across Technology - Making It Work

Kalpesh D. Mehta, Raghuram S. Tupuri, Soumitra De Sirkar, 1992, The Fifth International Conference on VLSI Design.

A novel hierarchical test generation method for processors

Jacob A. Abraham, Raghuram S. Tupuri, 1997, Proceedings Tenth International Conference on VLSI Design.

A novel functional test generation method for processors using commercial ATPG

Jacob A. Abraham, Raghuram S. Tupuri, J. Abraham, 1997, Proceedings International Test Conference 1997.

Test generation for Gigahertz processors using an automatic functional constraint extractor

Jacob A. Abraham, Raghuram S. Tupuri, Arun Krishnamachary, 1999, DAC '99.

A Robust Top-Down Dynamic Power Estimation Methodology for Delay Constrained Register Transfer Level Sequential Circuits

Jacob A. Abraham, Raghuram S. Tupuri, Sriram Sambamurthy, 2008, 21st International Conference on VLSI Design (VLSID 2008).

A Hierarchical Test Generation Approach Using Program Slicing Techniques on Hardware Description Languages

Jacob A. Abraham, Vivekananda M. Vedula, Jayanta Bhadra, 2003, J. Electron. Test..

A comprehensive fault model for deep submicron digital circuits

Jacob A. Abraham, Raghuram S. Tupuri, Arun Krishnamachary, 2002, Proceedings First IEEE International Workshop on Electronic Design, Test and Applications '2002.