Dinesh Pamunuwa

发表

Compact modelling of Through-Silicon Vias (TSVs) in three-dimensional (3-D) integrated circuits

Hannu Tenhunen, Li-Rong Zheng, Roshan Weerasekera, 2009, 2009 IEEE International Conference on 3D System Integration.

3-D integration and the limits of silicon computation

Axel Jantsch, Roshan Weerasekera, Matt Grange, 2011, 2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip.

Scalability of network-on-chip communication architecture for 3-D meshes

Axel Jantsch, Hannu Tenhunen, Zhonghai Lu, 2009, 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip.

Energy and Latency Optimization in NEM Relay-Based Digital Circuits

Antonios Bazigos, Adrian M. Ionescu, Tian Qin, 2014, IEEE Transactions on Circuits and Systems I: Regular Papers.

Optimising bandwidth over deep sub-micron interconnect

Hannu Tenhunen, Li-Rong Zheng, Dinesh Pamunuwa, 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

Modelling noise and delay in VLSI circuits

Hannu Tenhunen, Shauki Elassaad, Dinesh Pamunuwa, 2003 .

Early selection of system implementation choice among SoC, SoP and 3-D Integration

Hannu Tenhunen, Li-Rong Zheng, Roshan Weerasekera, 2007, 2007 IEEE International SOC Conference.

Minimal-Power, Delay-Balanced Smart Repeaters for Global Interconnects in the Nanometer Regime

Hannu Tenhunen, Li-Rong Zheng, Roshan Weerasekera, 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

2-D and 3-D Integration of Heterogeneous Electronic Systems under Cost, Performance and Technological Constraints

Hannu Tenhunen, Roshan Weerasekera, Dinesh Pamunuwa, 2009 .

Two-Dimensional and Three-Dimensional Integration of Heterogeneous Electronic Systems Under Cost, Performance, and Technological Constraints

Hannu Tenhunen, Li-Rong Zheng, Roshan Weerasekera, 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Signalling Techniques for DSM Designs

Li-Rong Zheng, Dinesh Pamunuwa, 2002 .

Application of Molecular Electronics Devices in Digital Circuit Design

Dinesh Pamunuwa, Ci Lei, Steven Bailey, 2008, NanoNet.

Design methodologies, models and tools for very-large-scale integration of NEM relay-based circuits

Tian Qin, Dinesh Pamunuwa, Sunil Rana, 2015, 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Analytic Modeling of Interconnects for Deep Sub-Micron Circuits

Hannu Tenhunen, Shauki Elassaad, Dinesh Pamunuwa, 2003, ICCAD 2003.

Analytic Modeling of Interconnects for Deep Sub-Micron Circuits

Hannu Tenhunen, Shauki Elassaad, Dinesh Pamunuwa, 2003, ICCAD.

On signalling over Through-Silicon Via (TSV) interconnects in 3-D Integrated Circuits

Hannu Tenhunen, Roshan Weerasekera, Matt Grange, 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

Layout, Performance and Power Trade-Offs in Mesh-Based Network-on-Chip Architectures

Axel Jantsch, Johnny Öberg, Li-Rong Zheng, 2003, VLSI-SOC.

Analytical Compact Model in Verilog-A for Electrostatically Actuated Ohmic Switches

Antonios Bazigos, Adrian M. Ionescu, Daniel Grogg, 2014, IEEE Transactions on Electron Devices.

A 6.7-GHz Active Gate Driver for GaN FETs to Combat Overshoot, Ringing, and EMI

Bernard H. Stark, Simon J. Hollis, Dinesh Pamunuwa, 2018, IEEE Transactions on Power Electronics.

Memory Technology for Extended Large-Scale Integration in Future Electronics Applications

Dinesh Pamunuwa, 2008, 2008 Design, Automation and Test in Europe.

Delay-Balanced Smart Repeaters for On-Chip Global Signaling

Hannu Tenhunen, Li-Rong Zheng, Roshan Weerasekera, 2007, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07).

On dynamic delay and repeater insertion in distributed capacitively coupled interconnects

Hannu Tenhunen, Dinesh Pamunuwa, H. Tenhunen, 2002, Proceedings International Symposium on Quality Electronic Design.

Modelling NEM relays for digital circuit applications

Tian Qin, Daniel Grogg, Yu Pu, 2013, 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013).

Minimal-power, delay-balanced smart repeaters for interconnects in the nanometer regime

Hannu Tenhunen, Li-Rong Zheng, Roshan Weerasekera, 2006, SLIP '06.

Combating digital noise in high speed ULSI circuits using binary BCH encoding

Hannu Tenhunen, Li-Rong Zheng, Dinesh Pamunuwa, 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

Bandwidth optimization for through silicon via (TSV) bundles in 3D integrated circuits.

Hannu Tenhunen, Li-Rong Zheng, Roshan Weerasekera, 2009 .

System Performance Analysis for Heterogeneous 3-D ICs and Emerging Technologies

Dinesh Pamunuwa, 2013 .

Shaping switching waveforms in a 650 V GaN FET bridge-leg using 6.7 GHz active gate drivers

Bernard H. Stark, Simon J. Hollis, Dinesh Pamunuwa, 2017, 2017 IEEE Applied Power Electronics Conference and Exposition (APEC).

Comparative Cost Analysis of 3-D Integrated Circuits

Axel Jantsch, Roshan Weerasekera, Matt Grange, 2011 .

Physical mapping and performance study of a multi-clock 3-Dimensional Network-on-Chip mesh

Axel Jantsch, Zhonghai Lu, Roshan Weerasekera, 2009, 2009 IEEE International Conference on 3D System Integration.

Optimal signaling techniques for Through Silicon Vias in 3-D integrated circuit packages

Matt Grange, Dinesh Pamunuwa, Roshan Weerasekera, 2010, 19th Topical Meeting on Electrical Performance of Electronic Packaging and Systems.

Switching Sensitive Driver Circuit to Combat Dynamic Delay in On-Chip Buses

Hannu Tenhunen, Li-Rong Zheng, Roshan Weerasekera, 2005, PATMOS.

Closed form metrics to accurately model the response in general arbitrarily-coupled RC trees

Shauki Elassaad, Dinesh Pamunuwa, 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

Exploration of Through-Silicon Via Interconnect Parasitics for 3-Dimensional Integrated Circuits

Hannu Tenhunen, Roshan Weerasekera, Matt Grange, 2009 .

Maximizing throughput over parallel wire structures in the deep submicrometer regime

Hannu Tenhunen, Li-Rong Zheng, Dinesh Pamunuwa, 2003, IEEE Trans. Very Large Scale Integr. Syst..

Performance Analysis of Nanoelectromechanical Relay-Based Field-Programmable Gate Arrays

Dinesh Pamunuwa, Sunil Rana, Frank Niklaus, 2018, IEEE Access.

On dynamic delay and repeater insertion

Hannu Tenhunen, Dinesh Pamunuwa, H. Tenhunen, 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

Designing Reliable Digital Molecular Electronic Circuits

Dinesh Pamunuwa, Ci Lei, Steven Bailey, 2009, NanoNet.

Extending systems-on-chip to the third dimension: performance, cost and technological tradeoffs

Hannu Tenhunen, Li-Rong Zheng, Roshan Weerasekera, 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.

The Promises and Limitations of 3-D Integration

Axel Jantsch, Matt Grange, Dinesh Pamunuwa, 2011, 3D Integration for NoC-based SoC Architectures.

Modeling the computational efficiency of 2-D and 3-D silicon processors for early-chip planning

Axel Jantsch, Roshan Weerasekera, Matt Grange, 2011, 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Wire-bonded through-silicon vias with low capacitive substrate coupling

Roshan Weerasekera, Dinesh Pamunuwa, Göran Stemme, 2011 .

Error-Control Coding to Combat Digital Noise in Interconnects for ULSI Circuits

Hannu Tenhunen, Li-Rong Zheng, Dinesh Pamunuwa, 1999 .

A scalable multi-dimensional NoC simulation model for diverse spatio-temporal traffic patterns

Axel Jantsch, Hannu Tenhunen, Matt Grange, 2013, 2013 IEEE International 3D Systems Integration Conference (3DIC).

Nanoelectromechanical (NEM) Relay-Based Computing

Dinesh Pamunuwa, D. Pamunuwa, 2016 .

A global wire planning scheme for Network-on-Chip

Jian Liu, Hannu Tenhunen, Li-Rong Zheng, 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

Modelling and analysis of interconnects for deep submicron systems-on-chip.

Dinesh Pamunuwa, D. Pamunuwa, 2003 .

Electromechanical design space exploration for electrostatically actuated ohmic switches using extended parallel plate compact model

Antonios Bazigos, Adrian M. Ionescu, Daniel Grogg, 2014 .

Zero-load predictive model for performance analysis in deflection routing NoCs

Axel Jantsch, Hannu Tenhunen, Matt Grange, 2015, Microprocess. Microsystems.

Optimal network architectures for minimizing average distance in k-ary n-dimensional mesh networks

Axel Jantsch, Roshan Weerasekera, Matt Grange, 2011, Proceedings of the Fifth ACM/IEEE International Symposium.

Repeater insertion to minimise delay in coupled interconnects

Hannu Tenhunen, Dinesh Pamunuwa, 2001, VLSI Design 2001. Fourteenth International Conference on VLSI Design.

Modeling delay and noise in arbitrarily coupled RC trees

Hannu Tenhunen, Shauki Elassaad, Dinesh Pamunuwa, 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Modeling the Efficiency of Stacked Silicon Systems: Computational, Thermal and Electrical Performance

Axel Jantsch, Roshan Weerasekera, Matt Grange, 2011, DATE 2011.

A study on the implementation of 2-D mesh-based networks-on-chip in the nanometre regime

Axel Jantsch, Hannu Tenhunen, Johnny Öberg, 2004, Integr..

Design of robust molecular electronic circuits

Dinesh Pamunuwa, Ci Lei, Steven Bailey, 2009, 2009 IEEE International Symposium on Circuits and Systems.