J. Postel-Pellerin

发表

Toward an innovative stochastic modeling of electric charges loss through dielectric

G. Micolau, J. Postel-Pellerin, P. Chiquet, 2016 .

Simulation of the programming efficiency and the energy consumption of Flash memories during endurance degradation

J. Postel-Pellerin, P. Chiquet, V. Della Marca, 2016, 2016 International Semiconductor Conference (CAS).

Electromagnetic Analysis Perturbation using Chaos Generator

Romain Wacquez, Philippe Maurine, J. Postel-Pellerin, 2016 .

A new non-volatile memory cell based on the flash architecture for embedded low energy applications: ATW (Asymmetrical Tunnel Window)

J. Postel-Pellerin, V. Della Marca, F. Lalande, 2014, 2014 International Semiconductor Conference (CAS).

A ful12D and 3D TCAD Simulation ofultimate 22nm NAND Flash Memories

B. Villard, R. Bouchakour, J. Postel-Pellerin, 2009 .

An evaluation of the extrinsic cells number in a memory array using cross-correlation products and deconvolution: an instance of a microelectronics experimental inverse problem

G. Micolau, J. Postel-Pellerin, R. Laffont, 2011 .

Charge loss activation during non-volatiles memory data retention

G. Micolau, J. Postel-Pellerin, P. Chiquet, 2012, CAS 2012 (International Semiconductor Conference).

ReRAM ON/OFF resistance ratio degradation due to line resistance combined with device variability in 28nm FDSOI technology

J. Postel-Pellerin, M. Bocquet, J.-M. Portal, 2017, 2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS).

Improving Flash memory endurance and consumption with ultra-short channel-hot-electron programming pulses

J. Postel-Pellerin, P. Chiquet, V. Della Marca, 2014, 2014 International Semiconductor Conference (CAS).

Integrated reliability in EEPROM nonvolatile memory cell design

R. Bouchakour, J. Postel-Pellerin, F. Lalande, 2004, Proceedings. 2004 IEEE Computational Systems Bioinformatics Conference.

Access resistor modelling for EEPROM's retention test vehicle

J. Postel-Pellerin, P. Canet, Jean-Luc Ogier, 2013, Microelectron. Reliab..

A full 2D and 3D TCAD simulation of ultimate 22nm NAND Flash memories

B. Villard, R. Bouchakour, J. Postel-Pellerin, 2009, 2009 10th Annual Non-Volatile Memory Technology Symposium (NVMTS).

Robustness of the floating-gate technique in a very low-noise environment

G. Micolau, J. Postel-Pellerin, P. Chiquet, 2014, 2014 International Semiconductor Conference (CAS).

Impact of Line Resistance Combined with Device Variability on Resistive RAM Memories

J. Postel-Pellerin, P. Canet, Hassan Aziza, 2018 .

Optimization of programming consumption of silicon nanocrystal memories for low power applications

P. Boivin, S. Deleonibus, J. Postel-Pellerin, 2012, 2012 International Semiconductor Conference Dresden-Grenoble (ISCDG).