Linda S. Milor

发表

AVERT: An elaborate model for simulating variable retention time in DRAMs

Soonyoung Cha, Daehyun Kim, Linda S. Milor, 2015, Microelectron. Reliab..

Comprehensive reliability and aging analysis on SRAMs within microprocessor systems

Chang-Chih Chen, Taizhi Liu, Linda S. Milor, 2015, Microelectron. Reliab..

Accurate standard cell characterization and statistical timing analysis using multivariate adaptive regression splines

Chang-Chih Chen, Taizhi Liu, Linda S. Milor, 2015, Sixteenth International Symposium on Quality Electronic Design.

Impact of NBTI/PBTIon SRAMs within microprocessor systems: Modeling, simulation, and analysis

Chang-Chih Chen, Linda S. Milor, Fahad Ahmed, 2013, Microelectron. Reliab..

Optimal Accelerated Test Regions for Time- Dependent Dielectric Breakdown Lifetime Parameters Estimation in FinFET Technology

Taizhi Liu, Rui Zhang, Dae-Hyun Kim, 2018, 2018 Conference on Design of Circuits and Integrated Systems (DCIS).

Reliable cache design with on-chip monitoring of NBTI degradation in SRAM cells using BIST

Linda S. Milor, Fahad Ahmed, 2010, 2010 28th VLSI Test Symposium (VTS).

Built-in self-test for bias temperature instability, hot-carrier injection, and gate oxide breakdown in embedded DRAMs

Soonyoung Cha, Daehyun Kim, Linda S. Milor, 2015, Microelectron. Reliab..

A bist solution for the test of I/O speed

Linda S. Milor, Cheng Jia, 2003, International Test Conference, 2003. Proceedings. ITC 2003..

Circuit-level reliability simulator for front-end-of-line and middle-of-line time-dependent dielectric breakdown in FinFET technology

Taizhi Liu, Rui Zhang, Kexin Yang, 2018, 2018 IEEE 36th VLSI Test Symposium (VTS).

Impact of spatial intrachip gate length variability on theperformance of high-speed digital circuits

Kurt Keutzer, Linda S. Milor, Michael Orshansky, 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Simulation of system backend dielectric reliability

Chang-Chih Chen, Sung Kyu Lim, Daehyun Kim, 2014, Microelectron. J..

MBIST and statistical hypothesis test for time dependent dielectric breakdowns due to GOBD vs. BTDDB in an SRAM array

Chang-Chih Chen, Soonyoung Cha, Linda S. Milor, 2015, 2015 IEEE 33rd VLSI Test Symposium (VTS).

A BIST Circuit for DLL Fault Detection

Linda S. Milor, Cheng Jia, 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Timing Analysis with Compact Variation-Aware Standard Cell Models

Linda S. Milor, Seyed-Abdollah Aftabjahani, 2009, CSIE.

Analysis of the layout impact on electric fields in interconnect structures using finite element method

Linda S. Milor, Changsoo Hong, M. Z. Lin, 2004, Microelectron. Reliab..

Fast Variation-Aware Statistical Dynamic Timing Analysis

Linda S. Milor, Seyed-Abdollah Aftabjahani, 2009, 2009 WRI World Congress on Computer Science and Information Engineering.

Via wearout detection with on chip monitors

Linda S. Milor, Fahad Ahmed, 2009, 2009 3rd International Workshop on Advances in sensors and Interfaces.

A DLL Design for Testing I/O Setup and Hold Times

Linda S. Milor, Cheng Jia, L. Milor, 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Impact of systematic spatial intra-chip gate length variability on performance of high-speed digital circuits

Kurt Keutzer, Linda S. Milor, Michael Orshansky, 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

Analysis and On-Chip Monitoring of Gate Oxide Breakdown in SRAM Cells

Linda S. Milor, Fahad Ahmed, 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

On-line monitoring of system health using on-chip SRAMs as a wearout sensor

Taizhi Liu, Linda S. Milor, Woongrae Kim, 2017, 2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS).

An efficient algorithm to determine the image of a parallelepiped under a linear transformation

Linda S. Milor, V. Visvanathan, 1986, SCG '86.

Estimation of the Optimal Accelerated Test Region for FinFET SRAMs Degraded by Front-End and Back-End Wearout Mechanisms

Taizhi Liu, Rui Zhang, Kexin Yang, 2018, 2018 Conference on Design of Circuits and Integrated Systems (DCIS).

Towards a chip level reliability simulator for copper/low-k backend processes

Linda S. Milor, Muhammad Bashir, 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

Wearout-aware compiler-directed register assignment for embedded systems

David Atienza, Mohamed M. Sabry, Linda S. Milor, 2012, Thirteenth International Symposium on Quality Electronic Design (ISQED).

Modeling of the breakdown mechanisms for porous copper/low-k process flows

Linda S. Milor, Changsoo Hong, 2007, Microelectron. Reliab..

Statistical model of NBTI and reliability simulation for analogue circuits

Shiyuan Yang, Linda S. Milor, Zhengliang Lv, 2012, Microelectron. Reliab..

Front-end of line and middle-of-line time-dependent dielectric breakdown reliability simulator for logic circuits

Taizhi Liu, Rui Zhang, Dae-Hyun Kim, 2017, Microelectron. Reliab..

Study of Area Scaling Effect on Integrated Circuit Reliability Based on Yield Models

Linda S. Milor, Tom Lin, Munkang Choi, 2005, Microelectron. Reliab..

Microprocessor Aging Analysis and Reliability Modeling Due to Back-End Wearout Mechanisms

Chang-Chih Chen, Linda S. Milor, L. Milor, 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Memory yield and lifetime estimation considering aging errors

Dae-Hyun Kim, Linda S. Milor, 2015, 2015 IEEE International Integrated Reliability Workshop (IIRW).

Computing parametric yield adaptively using local linear models

Linda S. Milor, Mien Li, 1996, DAC '96.

Panel: Analog/RF BIST: Are we there yet?

Sule Ozev, Linda S. Milor, 2015, 2015 IEEE 33rd VLSI Test Symposium (VTS).

Detection of catastrophic faults in analog integrated circuits

Linda S. Milor, V. Visvanathan, V. Visvanathan, 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Extraction of threshold voltage degradation modeling due to Negative Bias Temperature Instability in circuits with I/O measurements

Chang-Chih Chen, Taizhi Liu, Soonyoung Cha, 2014, 2014 IEEE 32nd VLSI Test Symposium (VTS).

Diagnosis of Optical Lithography Faults With Product Test Sets

Linda S. Milor, Munkang Choi, 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

System-level estimation of threshold voltage degradation due to NBTI with I/O measurements

Chang-Chih Chen, Soonyoung Cha, Linda S. Milor, 2014, 2014 IEEE International Reliability Physics Symposium.

Backend Dielectric Reliability Full Chip Simulator

Chang-Chih Chen, Sung Kyu Lim, Daehyun Kim, 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Is High Frequency Analog DFT Possible?

Bozena Kaminska, Linda S. Milor, Jérôme Wojcik, 1996, VTS.

SRAM stability analysis for different cache configurations due to Bias Temperature Instability and Hot Carrier Injection

Chang-Chih Chen, Taizhi Liu, Linda S. Milor, 2016, 2016 IEEE 34th International Conference on Computer Design (ICCD).

Minimizing production test time to detect faults in analog circuits

Alberto L. Sangiovanni-Vincentelli, Linda S. Milor, A. Sangiovanni-Vincentelli, 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

ECC-ASPIRIN: An ECC-assisted post-package repair scheme for aging errors in DRAMs

Daehyun Kim, Linda S. Milor, L. Milor, 2016, 2016 IEEE 34th VLSI Test Symposium (VTS).

Frontend wearout modeling from device to system with power/ground signature analysis

Chang-Chih Chen, Soonyoung Cha, Linda S. Milor, 2014, 2014 IEEE International Integrated Reliability Workshop Final Report (IIRW).

Analysis of errors in estimating wearout characteristics of time-dependent dielectric breakdown using system-level accelerated life test

Dae-Hyun Kim, Linda S. Milor, 2017, Microelectron. Reliab..

System-level variation-aware aging simulator using a unified novel gate-delay model for bias temperature instability, hot carrier injection, and gate oxide breakdown

Chang-Chih Chen, Taizhi Liu, Soonyoung Cha, 2015, Microelectron. Reliab..

Backend dielectric reliability simulator for microprocessor system

Chang-Chih Chen, Sung Kyu Lim, Daehyun Kim, 2012, Microelectron. Reliab..

Performance Modeling Using

Linda S. Milor, Chieh-Yuan Chao, L. Milor, 1995 .

Computing parametric yield accurately and efficiently

Alberto L. Sangiovanni-Vincentelli, Linda S. Milor, 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

Built-in self test methodology for diagnosis of backend wearout mechanisms in SRAM cells

Linda S. Milor, Woongrae Kim, 2014, 2014 IEEE 32nd VLSI Test Symposium (VTS).

Methodology to determine the impact of linewidth variation on chip scale copper/low-k backend dielectric breakdown

Sung Kyu Lim, Daehyun Kim, Linda S. Milor, 2010, Microelectron. Reliab..

Impact on circuit performance of deterministic within-die variation in nanoscale semiconductor manufacturing

Linda S. Milor, Munkang Choi, 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

System-Level Modeling of Microprocessor Reliability Degradation Due to Bias Temperature Instability and Hot Carrier Injection

Chang-Chih Chen, Taizhi Liu, Linda S. Milor, 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A methodology to extract failure rates for low-k dielectric breakdown with multiple geometries and in the presence of die-to-die linewidth variation

Linda S. Milor, Muhammad Bashir, 2009, Microelectron. Reliab..

Timing Analysis with Compact Variation-Aware Standard Cell Models

Linda S. Milor, Seyed-Abdollah Aftabjahani, L. Milor, 2009, 2009 WRI World Congress on Computer Science and Information Engineering.

Online Measurement of Degradation Due to Bias Temperature Instability in SRAMs

Linda S. Milor, Fahad Ahmed, L. Milor, 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Compact Variation-Aware Standard Cell Models for Timing Analysis - Complexity and Accuracy Analysis

Linda S. Milor, Seyed-Abdollah Aftabjahani, 2008, 9th International Symposium on Quality Electronic Design (isqed 2008).

A Delay Evaluation Circuit for Analog BIST Function

Hong Wang, Shiyuan Yang, Linda S. Milor, 2013, IEICE Trans. Electron..

Impact of NBTI on analog components

Shiyuan Yang, Linda S. Milor, Zhengliang Lv, 2012, 2012 17th IEEE European Test Symposium (ETS).

Modeling Low-k Dielectric Breakdown to Determine Lifetime Requirements

Linda S. Milor, Muhammad Bashir, L. Milor, 2009, IEEE Design & Test of Computers.

Backend dielectric breakdown dependence on linewidth and pattern density

Linda S. Milor, Changsoo Hong, 2007, Microelectron. Reliab..

The die-to-die calibrated combined model of negative bias temperature instability and gate oxide breakdown from device to system

Taizhi Liu, Soonyoung Cha, Daehyun Kim, 2015, Microelectron. Reliab..

Impact of irregular geometries on low-k dielectric breakdown

Sung Kyu Lim, Daehyun Kim, Linda S. Milor, 2011, Microelectron. Reliab..

System-level modeling and microprocessor reliability analysis for backend wearout mechanisms

Chang-Chih Chen, Linda S. Milor, 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

A methodology for estimating memory lifetime using a system-level accelerated life test and error-correcting codes

Dae-Hyun Kim, Linda S. Milor, 2017, 2017 IEEE 35th VLSI Test Symposium (VTS).

Reliable cache design with detection of gate oxide breakdown using BIST

Linda S. Milor, Fahad Ahmed, 2009, 2009 IEEE International Conference on Computer Design.

A comparative study of wearout mechanisms in state-of-art microprocessors

Chang-Chih Chen, Linda S. Milor, Fahad Ahmed, 2012, 2012 IEEE 30th International Conference on Computer Design (ICCD).

Built-In Self-Test Methodology With Statistical Analysis for Electrical Diagnosis of Wearout in a Static Random Access Memory Array

Chang-Chih Chen, Linda S. Milor, Woongrae Kim, 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.