Andrew Ferraiuolo

发表

Timing channel protection for a shared memory controller

Yao Wang, Andrew Ferraiuolo, G. Edward Suh, 2014, HPCA.

Videos of demo of self-driving robot with map verification

Andrew Ferraiuolo, G. Edward Suh, Andrew C. Myers, 2017 .

Lattice priority scheduling: Low-overhead timing-channel protection for a shared memory controller

Andrew Ferraiuolo, G. Edward Suh, Danfeng Zhang, 2014, 2016 IEEE International Symposium on High Performance Computer Architecture (HPCA).

Secure Autonomous Cyber-Physical Systems Through Verifiable Information Flow Control

Andrew Ferraiuolo, G. Edward Suh, Mark E. Campbell, 2018, CPS-SPC@CCS.

HyperFlow: A Processor Architecture for Nonmalleable, Timing-Safe Information Flow Security

Andrew Ferraiuolo, G. Edward Suh, Andrew C. Myers, 2018, CCS.

Secure information flow verification with mutable dependent types

Andrew Ferraiuolo, G. Edward Suh, Andrew C. Myers, 2017, 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC).

Komodo: Using verification to disentangle secure-enclave hardware from software

Andrew Ferraiuolo, Chris Hawblitzel, Andrew Baumann, 2017, SOSP.

Security Results for SIRRTL, A Hardware Description Language for Information Flow Security

Andrew Ferraiuolo, 2017 .

Low-overhead and high coverage run-time race detection through selective meta-data management

Andrew Ferraiuolo, G. Edward Suh, Ruirui C. Huang, 2014, 2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA).

Detection of trojans using a combined ring oscillator network and off-chip transient power analysis

Mark Mohammad Tehranipoor, Andrew Ferraiuolo, Xuehui Zhang, 2013, JETC.

Verification of a practical hardware security architecture

Andrew Ferraiuolo, G. Edward Suh, Danfeng Zhang, 2016, International Conference on Architectural Support for Programming Languages and Operating Systems.

Detecting Hardware Trojans using On-chip Sensors in an ASIC Design

Mark Mohammad Tehranipoor, Andrew Ferraiuolo, Xuehui Zhang, 2015, J. Electron. Test..

Full-Processor Timing Channel Protection with Applications to Secure Hardware Compartments

Andrew Ferraiuolo, Danfeng Zhang, Rui Xu, 2017 .

HyperFlow: A Processor Architecture for Timing-Safe Information-Flow Security

Andrew Ferraiuolo, G. Edward Suh, Andrew C. Myers, 2018 .

Experimental analysis of a ring oscillator network for hardware Trojan detection in a 90nm ASIC

Mark Mohammad Tehranipoor, Andrew Ferraiuolo, Xuehui Zhang, 2012, 2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

SecDCP: Secure dynamic cache partitioning for efficient timing channel protection

Andrew Ferraiuolo, G. Edward Suh, Danfeng Zhang, 2016, 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC).

Verification of a Practical Hardware Security Architecture Through Static Information Flow Analysis

Rui Xu, Andrew Ferraiuolo, G. Edward Suh, 2017, ASPLOS.

Lightweight Verification of Secure Hardware Isolation Through Static Information Flow Analysis (Technical Report)

Andrew Ferraiuolo, G. Edward Suh, Danfeng Zhang, 2017 .