Kun-Yung Ken Chang

A 0.4-4-Gb/s CMOS quad transceiver cell using on-chip regulated dual-loop PLLs

Mark Horowitz, Simon Li, Stefanos Sidiropoulos, 2003 .

A 16 Gb/s/Link, 64 GB/s Bidirectional Asymmetric Memory Interface

Ting Wu, J. Zerbe, W.T. Beyene, 2009, IEEE Journal of Solid-State Circuits.

A 50 Gb / s CMOS Crossbar Chip using Asymmetric Serial Links *

Nick McKeown, Mark Horowitz, Shang-Tse Chuang, .