Emna Amouri

发表

On Exploiting Partitioning-Based Placement Approach for Performances Improvement of 3D FPGA

Mohamed Abid, Zied Marrakchi, Habib Mehrez, 2017, 2017 International Conference on High Performance Computing & Simulation (HPCS).

Performance analysis and optimization of cluster-based mesh FPGA architectures: design methodology and CAD tool support

Mohamed Abid, Zied Marrakchi, Habib Mehrez, 2017, Turkish J. Electr. Eng. Comput. Sci..

Design of advanced 2D and 3D FPGAs: Architecture-level exploration and algorithm-level optimization

Mohamed Abid, Zied Marrakchi, Habib Mehrez, 2016, 2016 11th International Design & Test Symposium (IDT).

Improvement of cluster-based Mesh FPGA architecture using novel hierarchical interconnect topology and long routing wires

Zied Marrakchi, Habib Mehrez, Vinod Pangracious, 2016, Microprocess. Microsystems.

Exploration of Mesh-Based FPGA Architecture: Comparison of 2D and 3D Technologies in Terms of Power, Area and Performance

Mohamed Abid, Zied Marrakchi, Habib Mehrez, 2016, 2016 24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP).

Countering early propagation and routing imbalance of DPL designs in a tree-based FPGA

Jean-Luc Danger, Shivam Bhasin, Emna Amouri, 2015, 2015 International Conference on IC Design & Technology (ICICDT).

Mesh of Clusters FPGA Architectures: Exploration Methodology and Interconnect Optimization

Mohamed Abid, Zied Marrakchi, Habib Mehrez, 2015, ARC.

Three-dimensional Mesh of Clusters: An alternative unified high performance interconnect architecture for 3D-FPGA implementation

Mohamed Abid, Zied Marrakchi, Habib Mehrez, 2014, 2014 International 3D Systems Integration Conference (3DIC).

Balancing WDDL dual-rail logic in a tree-based FPGA to enhance physical security

Habib Mehrez, Jean-Luc Danger, Shivam Bhasin, 2014, 2014 24th International Conference on Field Programmable Logic and Applications (FPL).

Impact of Cluster Size on Routability, Testability and Robustness of a Cluster in a Mesh FPGA

Zied Marrakchi, Habib Mehrez, Lorena Anghel, 2014, 2014 IEEE Computer Society Annual Symposium on VLSI.

Efficient multilevel interconnect topology for cluster-based mesh FPGA architecture

Zied Marrakchi, Habib Mehrez, Adrien Blanchardon, 2013, 2013 International Conference on Reconfigurable Computing and FPGAs (ReConFig).

A defect-tolerant cluster in a mesh SRAM-based FPGA

Zied Marrakchi, Habib Mehrez, Mounir Benabdenbi, 2013, 2013 International Conference on Field-Programmable Technology (FPT).

Performance Analysis and Optimization of High Density Tree-Based 3D Multilevel FPGA

Zied Marrakchi, Habib Mehrez, Vinod Pangracious, 2013, ARC.

Differential pair routing to balance dual signals of WDDL designs in cluster-based Mesh FPGA

Zied Marrakchi, Habib Mehrez, Emna Amouri, 2011, 6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC).

Security-centric FPGA CAD tools to balance dual-rail routing INWDDL designs

Zied Marrakchi, Habib Mehrez, Emna Amouri, 2011, 2011 VII Southern Conference on Programmable Logic (SPL).

Controlled placement and routing techniques to improve timing balance of WDDL designs in Mesh-based FPGA

Zied Marrakchi, Habib Mehrez, Emna Amouri, 2010, 2010 IEEE Asia Pacific Conference on Circuits and Systems.

Impact of dual placement on WDDL design security in Mesh-based and Tree-based FPGAs

Zied Marrakchi, Habib Mehrez, Emna Amouri, 2010, 6th Conference on Ph.D. Research in Microelectronics & Electronics.

Improving the Security of Dual Rail Logic in FPGA Using Controlled Placement and Routing

Zied Marrakchi, Hayder Mrabet, Habib Mehrez, 2009, 2009 International Conference on Reconfigurable Computing and FPGAs.

Placement and routing techniques to improve delay balance of WDDL netlist in MFPGA

Zied Marrakchi, Hayder Mrabet, Habib Mehrez, 2009, 2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009).

Performance analysis and optimization of high density tree-based 3 d multilevel FPGA

H. Mehrez, Z. Marrakchi, V. Pangracious, 2018 .

Impact of Dual Placement and Routing on WDDL Netlist Security in FPGA

Zied Marrakchi, Habib Mehrez, Emna Amouri, 2013, Int. J. Reconfigurable Comput..

Efficient tree topology for FPGA interconnect network

Zied Marrakchi, Hayder Mrabet, Habib Mehrez, 2008, ACM Great Lakes Symposium on VLSI.