Sergey V. Rylov

发表

A 10-Gb/s CMOS clock and data recovery circuit using a secondary delay-locked loop

Woogeun Rhee, Herschel A. Ainspan, Daniel J. Friedman, 2003, Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003..

A 25 Gb/s burst-mode receiver for low latency photonic switch networks

Mounir Meghelli, Alexander V. Rylyakov, Sergey V. Rylov, 2015, 2015 Optical Fiber Communications Conference and Exhibition (OFC).

A 1.4-pJ/b, power-scalable 16×12-Gb/s source-synchronous I/O with DFE receiver in 32nm SOI CMOS technology

Alexander V. Rylyakov, Seongwon Kim, Herschel A. Ainspan, 2014, Proceedings of the IEEE 2014 Custom Integrated Circuits Conference.

3.1 A 25Gb/s ADC-based serial line receiver in 32nm CMOS SOI

Yong Liu, Thomas Toifl, Mounir Meghelli, 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

RSFQ logic arithmetic

Sergey V. Rylov, Oleg A. Mukhanov, V. K. Semonov, 1989 .

Progress in the Development of a Superconductive High-Resolution ADC

Sergey V. Rylov, A. Polyakov, T. V. Filippov, 1999 .

An Adaptively Pipelined Mixed Synchronous-Asynchronous Digital FIR Filter Chip Operating at 1.3 Gigahertz

Alexander V. Rylyakov, Steven M. Nowick, Montek Singh, 2002, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32-nm SOI CMOS Technology

Thomas Toifl, Christian Menolfi, Andrea Prati, 2012, IEEE Journal of Solid-State Circuits.

A 78mW 11.1Gb/s 5-tap DFE receiver with digitally calibrated current-integrating summers in 65nm CMOS

Herschel A. Ainspan, Daniel J. Friedman, Sergey V. Rylov, 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

eal-Ti ita1 Error Correction for Flash An~~og-To-~i~ita l Converter

Sergey V. Rylov, Steven B. Kaplan, Paul D. Bradley, 1997 .

An 8x 10-Gb/s Source-Synchronous I/O System Based on High-Density Silicon Carrier Interconnects

Yong Liu, Xiaoxiong Gu, Herschel A. Ainspan, 2012, IEEE Journal of Solid-State Circuits.

Clockless Dynamic SFQ and Gate With High Input Skew Tolerance

Sergey V. Rylov, 2019, IEEE Transactions on Applied Superconductivity.

A 16-Gb/s Backplane Transceiver With 12-Tap Current Integrating DFE and Dynamic Adaptation of Voltage Offset and Timing Drifts in 45-nm SOI CMOS Technology

Mounir Meghelli, Michael A. Sorna, Sergey V. Rylov, 2012, IEEE J. Solid State Circuits.

An Adaptively Pipelined Mixed Synchronous-Asynchronous Digital FIR Filter Chip Operating at 1.3 Gigahertz

Alexander V. Rylyakov, Steven M. Nowick, Montek Singh, 2010, IEEE Trans. Very Large Scale Integr. Syst..

A 5.4mW 0.0035mm2 0.48psrms-jitter 0.8-to-5GHz non-PLL/DLL all-digital phase generator/rotator in 45nm SOI CMOS

Seongwon Kim, Daniel J. Friedman, Sergey V. Rylov, 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

A 28Gb/s 4-tap FFE/15-tap DFE serial link transceiver in 32nm SOI CMOS technology

Thomas Toifl, Christian Menolfi, Andrea Prati, 2012, 2012 IEEE International Solid-State Circuits Conference.

A 16-Gb/s backplane transceiver with 12-tap current integrating DFE and dynamic adaptation of voltage offset and timing drifts in 45-nm SOI CMOS technology

Mounir Meghelli, Sergey V. Rylov, Jong-Ru Guo, 2011, 2011 IEEE Custom Integrated Circuits Conference (CICC).

10+ Gb/s 90nm CMOS serial link demo in CBGA package

Thomas Zwick, Scott K. Reynolds, Sergey V. Rylov, 2004, Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571).

A 2.6mW 370MHz-to-2.5GHz Open-Loop Quadrature Clock Generator

Seongwon Kim, Daniel J. Friedman, Sergey V. Rylov, 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

A 32 Gb/s, 4.7 pJ/bit Optical Link With −11.7 dBm Sensitivity in 14-nm FinFET CMOS

Mounir Meghelli, Zeynep Toprak-Deniz, Seongwon Kim, 2018, IEEE Journal of Solid-State Circuits.

22.1 A 25Gb/s burst-mode receiver for rapidly reconfigurable optical networks

Mounir Meghelli, Alexander V. Rylyakov, Sergey V. Rylov, 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

High resolution ADV system

Sergey V. Rylov, R. P. Robertazzi, Lewis A. Bunz, 1999 .

osephson Output Interfaces for RSPQ Circuits

Sergey V. Rylov, D. V. Gaidarenko, A. Mukhanov, 1997 .

A 25 Gb/s Burst-Mode Receiver for Low Latency Photonic Switch Networks

Mounir Meghelli, Alexander V. Rylyakov, Sergey V. Rylov, 2015, IEEE Journal of Solid-State Circuits.

Experimental implementation of analog-to-digital converter based on the reversible ripple counter

Sergey V. Rylov, Konstantin K. Likharev, Oleg A. Mukhanov, 1991 .

Reversible conveyer computation in array of parametric quantrons

Sergey V. Rylov, Konstantin K. Likharev, Vasili K. Semenov, 1985 .

Josephson junction A/D converters using differential coding

Sergey V. Rylov, Konstantin K. Likharev, Vasili K. Semenov, 1987 .

Analysis of high-performance counter-type A/D converters using RSFQ logic/memory elements

Sergey V. Rylov, 1991 .

A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology

Alexander V. Rylyakov, Herschel A. Ainspan, Daniel J. Friedman, 2015, IEEE Journal of Solid-State Circuits.

Real-time digital error correction for flash analog-to-digital converter

Sergey V. Rylov, Steven B. Kaplan, Paul D. Bradley, 1997 .