Michael P. Beakes

发表

A 10-Gb/s CMOS clock and data recovery circuit using a secondary delay-locked loop

Woogeun Rhee, Herschel A. Ainspan, Daniel J. Friedman, 2003, Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003..

Single-chip 622-Mb/s SDH/SONET framer, digital cross-connect and add/drop multiplexer solution

David J. Webb, Scott K. Reynolds, Andreas Herkersdorf, 2001 .

A 25 Gb/s burst-mode receiver for low latency photonic switch networks

Mounir Meghelli, Alexander V. Rylyakov, Sergey V. Rylov, 2015, 2015 Optical Fiber Communications Conference and Exhibition (OFC).

A 6.4-Gb/s CMOS SerDes core with feed-forward and decision-feedback equalization

Michael A. Sorna, Herschel A. Ainspan, Michael P. Beakes, 2005, IEEE Journal of Solid-State Circuits.

A 3.5pJ/bit 8-tap-feed-forward 8-tap-decision feedback digital equalizer for 16Gb/s I/Os

Thomas Toifl, Christian Menolfi, Michael P. Beakes, 2014, ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC).

3.1 A 25Gb/s ADC-based serial line receiver in 32nm CMOS SOI

Yong Liu, Thomas Toifl, Mounir Meghelli, 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

A 78mW 11.1Gb/s 5-tap DFE receiver with digitally calibrated current-integrating summers in 65nm CMOS

Herschel A. Ainspan, Daniel J. Friedman, Sergey V. Rylov, 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

A 1.8 pJ/bit $16 \times 16\;\text{Gb/s}$ Source-Synchronous Parallel Interface in 32 nm SOI CMOS with Receiver Redundancy for Link Recalibration

Mounir Meghelli, Herschel A. Ainspan, Daniel J. Friedman, 2016, IEEE Journal of Solid-State Circuits.

An 8x 10-Gb/s Source-Synchronous I/O System Based on High-Density Silicon Carrier Interconnects

Yong Liu, Xiaoxiong Gu, Herschel A. Ainspan, 2012, IEEE Journal of Solid-State Circuits.

A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS

Aydin Babakhani, Jean-Olivier Plouchart, Alberto Valdes-Garcia, 2012, Proceedings of the IEEE 2012 Custom Integrated Circuits Conference.

A 23.5 GHz PLL With an Adaptively Biased VCO in 32 nm SOI-CMOS

Aydin Babakhani, Jean-Olivier Plouchart, Alberto Valdes-Garcia, 2013, IEEE Transactions on Circuits and Systems I: Regular Papers.

A 3.2GS/s 4.55b ENOB two-step subranging ADC in 45nm SOI CMOS

Jean-Olivier Plouchart, Scott K. Reynolds, Daniel J. Friedman, 2012, Proceedings of the IEEE 2012 Custom Integrated Circuits Conference.

22.1 A 25Gb/s burst-mode receiver for rapidly reconfigurable optical networks

Mounir Meghelli, Alexander V. Rylyakov, Sergey V. Rylov, 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS

Mounir Meghelli, Zeynep Toprak-Deniz, Herschel A. Ainspan, 2020, IEEE Journal of Solid-State Circuits.

A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology

Alexander V. Rylyakov, Herschel A. Ainspan, Daniel J. Friedman, 2015, IEEE Journal of Solid-State Circuits.

TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip

Bernard Brezzo, Gi-Joon Nam, Dharmendra S. Modha, 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A 7Gb/s 9.3mW 2-Tap Current-Integrating DFE Receiver

John Bulzacchelli, Michael P. Beakes, Daniel Friedman, 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

Multi-Wavelength Optical Transceivers Integrated on Node (MOTION)

Wooram Lee, Mounir Meghelli, Xiaoxiong Gu, 2019, 2019 Optical Fiber Communications Conference and Exhibition (OFC).

A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS

Michael P. Beakes, M. Meghelli, H. Ainspan, 2020, IEEE Journal of Solid-State Circuits.