Farah Naz Taher

A Low-Power Analog Bus for On-Chip Digital Communication

Farah Naz Taher, 2013 .

A machine learning based hard fault recuperation model for approximate hardware accelerators

Farah Naz Taher, Joseph Callenes-Sloan, Benjamin Carrión Schäfer, 2018, DAC.

Learning-Based Diversity Estimation: Leveraging the Power of High-Level Synthesis to Mitigate Common-Mode Failure

Farah Naz Taher, Benjamin Carrión Schäfer, Anjana Balachandran, 2019, 2019 IEEE 37th International Conference on Computer Design (ICCD).

Exploring Design Trade-offs in Fault-Tolerant Behavioral Hardware Accelerators

Farah Naz Taher, Benjamin Carrión Schäfer, Zhiqi Zhu, 2019, ACM Great Lakes Symposium on VLSI.

Design and Optimization of Reliable Hardware Accelerators: Leveraging the Advantages of High-Level Synthesis

Farah Naz Taher, Benjamin Carrión Schäfer, Mostafa Kishani, 2018, 2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS).

Efficient Hardware Acceleration for Design Diversity Calculation to Mitigate Common Mode Failures

Farah Naz Taher, Benjamin Carrión Schäfer, Anjana Balachandran, 2019, 2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

A Machine Learning based Hard Fault Recuperation Model for Approximate Hardware Accelerators

Farah Naz Taher, Benjamin Carrión Schäfer, Benjamin Carrion Schafer, 2018, 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC).

Common-Mode Failure Mitigation: Increasing Diversity through High-Level Synthesis

Farah Naz Taher, Benjamin Carrión Schäfer, Anjana Balachandran, 2019, 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Hardware Fault Compensation Using Discriminative Learning

Farah Naz Taher, Joseph Callenes-Sloan, Joseph Callenes-Sloan, 2015, 2015 IEEE 21st Pacific Rim International Symposium on Dependable Computing (PRDC).