N. Oda

Chip-level performance improvement using triple damascene wiring design concept for 0.13 /spl mu/m CMOS devices

A. Matsumoto, N. Oda, T. Yokoyama, 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

Chip-level performance maximization using ASIS (application-specific interconnect structure) wiring design concept for 45 nm CMOS devices

S. Ohnishi, N. Kawahara, Y. Kakuhara, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..