Vincenzo Izzo

A multi Gbit/s backplane for the RPC DAQ and L1 Trigger of the ATLAS Muon Spectrometer

A. Aloisio, Francesco Cevenini, L. Capasso, 2009 .

VLSI implementation of greedy-based distributed routing schemes for ad hoc networks

Salvatore Rampone, Alberto Aloisio, Vincenzo Izzo, 2007, Soft Comput..

Do's and don'ts with the Agilent's G-Link chipset

Francesco Cevenini, Alberto Aloisio, Vincenzo Izzo, 2005 .

Fast Control and Timing distribution based on FPGA-embedded serial Transceivers

Raffaele Giordano, Alberto Aloisio, Vincenzo Izzo, 2009, 2009 IEEE Nuclear Science Symposium Conference Record (NSS/MIC).

Redundant-Configuration Scrubbing of SRAM-Based FPGAs

Raffaele Giordano, Alberto Aloisio, Sabrina Perrella, 2017, IEEE Transactions on Nuclear Science.

A Service-Oriented Platform for Embedded Monitoring Systems in Belle II Experiment

A. Aloisio, F. Ameli, G. Tortone, 2017 .

Implementation of High-Resolution Time-to-Digital Converters on two different FPGA devices

S. Loffredo, Paolo Branchini, Vincenzo Izzo, 2008 .

Characterizing jitter performance of multi gigabit FPGA-embedded serial transceivers

Raffaele Giordano, Alberto Aloisio, Vincenzo Izzo, 2009, 2009 16th IEEE-NPSS Real Time Conference.

A high speed backplane for the RPC Read Out Driver of the ATLAS Muon Spectrometer

Raffaele Giordano, Alberto Aloisio, Adrian Jones, 2008, 2008 IEEE Nuclear Science Symposium Conference Record.

High‐Speed Deterministic‐Latency Serial IO

Alberto Aloisio, Raffaele Giordano, Vincenzo Izzo, 2017 .