Ali Jahanian

发表

Scalable security path methodology: A cost-security trade-off to protect FPGA IPs against active and passive tampers

Sharareh Zamanzadeh, Ali Jahanian, 2017, 2017 Asian Hardware Oriented Security and Trust Symposium (AsianHOST).

Efficient host-independent coprocessor architecture for speech coding algorithms

Hamid Noori, Mehdi Sedighi, Ali Jahanian, 2005, 8th Euromicro Conference on Digital System Design (DSD'05).

Using metro-on-chip in physical design flow for congestion and routability improvement

Morteza Saheb Zamani, Ali Jahanian, M. S. Zamani, 2008, Microelectron. J..

Multi-domain clock skew scheduling-aware register placement to optimize clock distribution network

Morteza Saheb Zamani, Naser MohammadZadeh, Ali Jahanian, 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

A CNT/Metal Hybrid Routing Architecture to Improve Performance of Ultra-Large FPGAs

Ali Jahanian, Mozhgan Malekshahi Rad, 2011 .

Improved timing closure by analytical buffer and TSV planning in three-dimensional chips

Ali Jahanian, Reza Abdollahi, 2012, IEICE Electron. Express.

Prediction and reduction of routing congestion

Morteza Saheb Zamani, Ali Jahanian, Mehdi Saeedi, 2006, ISPD '06.

Design of CAD ASIP for JIT extensible processor: Case study on PathFinder routing algorithm

Mohammad Eshghi, Ali Jahanian, Hassan Daryanavard, 2015, 2015 23rd Iranian Conference on Electrical Engineering.

Parallelizing the FPGA global routing algorithm on multi-core systems without quality degradation

Ali Jahanian, Arash Farkish, A. Jahanian, 2011, IEICE Electron. Express.

Multiplexed switch box architecture in three-dimensional FPGAs to reduce silicon area and improve TSV usage

Ali Jahanian, Marzieh Morshedzadeh, A. Jahanian, 2012, GLSVLSI '12.

Improved performance and yield with chip master planning design methodology

Morteza Saheb Zamani, Ali Jahanian, M. S. Zamani, 2009, GLSVLSI '09.

Performance Improvement and Congestion Reduction of Large FPGAs Using On-Chip Microwave Interconnects

Ali Jahanian, Adel Dokhanchi, Mohammad Taghi Teimoori, 2012, IEICE Trans. Electron..

Multi-threshold and multi-input DNA logic design style for profiling the microRNA biomarkers of real cancers.

Ali Jahanian, Mercedeh Sanjabi, A. Jahanian, 2019, IET nanobiotechnology.

Design Mining Color Semantics

Ali Jahanian, Ali Jahanian, 2016 .

Performance and Timing Yield Enhancement using Highway-on-Chip Planning

Morteza Saheb Zamani, Ali Jahanian, M. S. Zamani, 2008, 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools.

Trojan Vulnerability Map: An Efficient Metric for Modeling and Improving the Security Level of Hardware

Ali Jahanian, Mahmoud Bakhshizadeh, 2014, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Real parallel and constant delay logic circuit design methodology based on the DNA model-of-computation

Ali Jahanian, Z. Beiki, Z. Zare Dorabi, 2018, Microprocess. Microsystems.

Three-dimensional switchbox multiplexing in emerging 3D-FPGAs to reduce chip footprint and improve TSV usage

Ali Jahanian, Payam Pourashraf, Marzieh Morshedzadeh, 2015, Integr..

Layout Vulnerability Reduction against Trojan Insertion Using Security-Aware White Space Distribution

Ali Jahanian, Hamed Hossein-Talaee, 2017, 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

Security improvement of FPGA configuration file against the reverse engineering attack

Ali Jahanian, Sharareh ZamanZadeh, Shahram Shahabi, 2016, 2016 13th International Iranian Society of Cryptology Conference on Information Security and Cryptology (ISCISC).

Evaluating the Metro-on-Chip Methodology to Improve the Congestion and Routability

Morteza Saheb Zamani, Ali Jahanian, Mehrdad Najibi, 2008 .

Three-Dimensional Physical Design Flow for Monolithic 3D-FPGAs to Improve Timing Closure and Chip Area

Ali Jahanian, Armin Belghadr, A. Jahanian, 2017, J. Circuits Syst. Comput..

Acceleration of Inter-Task Routing for JIT Compilation Reconfigurable Computing Platform Using Customized Processor

Ali Jahanian, Mohammad Eshghi, Seyedhassan Daryanavard, 2015 .

RF-Interconnect Resource Assignment and Placement Algorithms in Application Specific ICs to Improve Performance and Reduce Routing Congestion

Ali Jahanian, Bahareh Pourshirazi, 2012, 2012 15th Euromicro Conference on Digital System Design.

A fast placement algorithm for embedded just-in-time reconfigurable extensible processing platform

Ali Jahanian, H. Daryanavard, M. Eshghi, 2014, The Journal of Supercomputing.

Improved performance and resource usage of FPGA using resource-aware design; the case of a decimal array multiplier

Ali Jahanian, Saba Amanollahi, Adel Hosseiny, 2013, The 17th CSI International Symposium on Computer Architecture & Digital Systems (CADS 2013).

Redesigned CMOS (4; 2) compressor for fast binary multipliers

Ali Jahanian, Ghassem Jaberipur, Abdoreza Pishvaie, 2013, Canadian Journal of Electrical and Computer Engineering.

VMAP: A Variation Map-Aware Placement Algorithm for Leakage Power Reduction in FPGAs

Morteza Saheb Zamani, Behzad Salami, Ali Jahanian, 2011, 2011 14th Euromicro Conference on Digital System Design.

Metro-on-chip: an efficient physical design technique for congestion reduction

Morteza Saheb Zamani, Ali Jahanian, M. S. Zamani, 2007, IEICE Electron. Express.

Area efficient, low power and robust design for add-compare-select units

Mohammad Kazem Akbari, Ali Jahanian, Bahman Javadi, 2004 .

Improved CMOS (4; 2) compressor designs for parallel multipliers

Ali Jahanian, Ghassem Jaberipur, Abdoreza Pishvaie, 2012, Comput. Electr. Eng..

Field-programmable cell array pin-constrained digital microfluidic biochip

Ali Jahanian, Alireza Abdoli, 2015, 2015 22nd Iranian Conference on Biomedical Engineering (ICBME).

Customized Placement Algorithm of Nanoscale DNA Logic Circuits

Ali Jahanian, Sedigheh Farhadtoosky, A. Jahanian, 2017, J. Circuits Syst. Comput..

Improved predictability, timing yield and power consumption using hierarchical highways-on-chip planning methodology

Morteza Saheb Zamani, Ali Jahanian, Hamid Safizadeh, 2011, Integr..

Web pages: What can you see in a single fixation?

Ali Jahanian, Ruth Rosenholtz, Shaiyan Keshvari, 2018, Cognitive research: principles and implications.

Design Mining Visual Balance

Ali Jahanian, Ali Jahanian, 2016 .

Drug Discovery Evolution Using the Customized Digital Microfluidic Biochips

Ali Jahanian, Maryam Taajobian, Shadi Momtahen, 2018, Electrical Engineering (ICEE), Iranian Conference on.

An Improved Standard Cell Placement Methodology using Hybrid Analytic and Heuristic Techniques

Morteza Saheb Zamani, Ali Jahanian, Esmaeil Khorram, 2010 .

Evaluation, prediction and reduction of routing congestion

Morteza Saheb Zamani, Ali Jahanian, Mehdi Saeedi, 2007, Microelectron. J..

Security Path: An Emerging Design Methodology to Protect the FPGA IPs Against Passive/Active Design Tampering

Sharareh Zamanzadeh, Ali Jahanian, 2016, J. Electron. Test..

Automatic magazine cover design

Ali Jahanian, Ali Jahanian, 2011 .

A Hybrid RF/Metal Clock Routing Algorithm to Improve Clock Delay and Routing Congestion

Ali Jahanian, Zohre Mohammadi-Arfa, 2011, 2011 IEEE Computer Society Annual Symposium on VLSI.

Performance Improvement of Physical Retiming with Shortcut Insertion

Morteza Saheb Zamani, Ali Jahanian, Adel Dokhanchi, 2008, 2008 IEEE Computer Society Annual Symposium on VLSI.

Fault-tolerant architecture and CAD algorithm for field-programmable pin-constrained digital microfluidic biochips

Ali Jahanian, Alireza Abdoli, A. Jahanian, 2015, 2015 CSI Symposium on Real-Time and Embedded Systems and Technologies (RTEST).

Metro-on-FPGA: A feasible solution to improve the congestion and routing resource management in future FPGAs

Ali Jahanian, Armin Belghadr, 2014, Integr..

Automatic netlist scrambling methodology in ASIC design flow to hinder the reverse engineering

Sharareh Zamanzadeh, Ali Jahanian, A. Jahanian, 2013, 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC).

Landmark-based Car Navigation with Overtake Capability in Multi-agent Environments

Ali Jahanian, Sirvan Khalighi, Mercedeh Sanjabi, 2012, ICAART.

Multi-level buffer block planning and buffer insertion for large design circuits

Morteza Saheb Zamani, Ali Jahanian, 2006, IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06).

A general-purpose field-programmable pin-constrained digital microfluidic biochip

Ali Jahanian, Alireza Abdoli, 2015, 2015 18th CSI International Symposium on Computer Architecture and Digital Systems (CADS).

Congestion and track usage improvement of large FPGAs using metro-on-FPGA methodology

Ali Jahanian, Mehdi Alipour, Mohammad Haji Seyed Javadi, 2011, GLSVLSI '11.

Self authentication path insertion in FPGA-based design flow for tamper-resistant purpose

Ali Jahanian, Sh. Zamanzadeh, 2016, ISC Int. J. Inf. Secur..

Area efficient, low power and robust design for add-compare-select units

Mohammad Kazem Akbari, Ali Jahanian, Bahman Javadi, 2004, Euromicro Symposium on Digital System Design, 2004. DSD 2004..

Chip master planning: An efficient methodology to improve design closure and complexity management of ultra large chips

Ali Jahanian, Morteza Saheb Zamani, A. Jahanian, 2010, 2010 15th CSI International Symposium on Computer Architecture and Digital Systems.

Efficient mapping of DNA logic circuits on parallelized digital microfluidic architcture

Ali Jahanian, Zohre Beiki, Maryam Taajobian, 2017, 2017 19th International Symposium on Computer Architecture and Digital Systems (CADS).

EJOP: An Extensible Java Processor with Reasonable Performance/Flexibility Trade-off

Ali Jahanian, Samaneh Talebi, Niloofar Abolghasemi, 2012, 2012 15th Euromicro Conference on Digital System Design.

Feasibility Study of Using the RF Interconnects in Large FPGAs to Improve Routing Tracks Usage

Ali Jahanian, Adel Dokhanchi, Esfandiar Mehrshahi, 2011, 2011 IEEE Computer Society Annual Symposium on VLSI.

Automatic Design of Self-Published Media: A Case Study of Magazine Covers

Ali Jahanian, Ali Jahanian, 2016 .

High-Performance General-Purpose Arithmetic Operations Using the Massive Parallel DNA-Based Computation

Ali Jahanian, Mercedeh Sanjabi, Maryam Tahmasebi, 2017, 2017 Euromicro Conference on Digital System Design (DSD).

Massive Parallel Digital Micro fluidic Biochip Architecture for Automating Large-Scale Biochemistry Assays

Ali Jahanian, Maryam Taajobian, Abbas Haddad, 2018 .

Improved Line Tracking System for Autonomous Navigation of High-Speed Vehicle

Ali Jahanian, Yahya Zare Khafri, 2012, ICRA 2012.

Improved timing closure by early buffer planning in floor-placement design flow

Morteza Saheb Zamani, Ali Jahanian, 2007, GLSVLSI '07.

RF resource planning in application specific integrated circuits to improve timing closure

Ali Jahanian, Ali Mohammad Zarei, 2013, The 17th CSI International Symposium on Computer Architecture & Digital Systems (CADS 2013).

Parallelizing the Coarsening Phase of Hyper-Edge Partitioning on the GPU Platform

Ali Jahanian, Atefeh Taheri, Behin Molaie, 2017 .

Higher security of ASIC fabrication process against reverse engineering attack using automatic netlist encryption methodology

Sharareh Zamanzadeh, Ali Jahanian, 2016, Microprocess. Microsystems.

Security-aware register placement to hinder malicious hardware updating and improve Trojan detectability

Ali Jahanian, Mehrshad Vosoughi, 2015, ISC Int. J. Inf. Secur..

Paint by Word pdf

Antonio Torralba, Aude Oliva, David Bau, 2021, ArXiv.

Generative Models as a Data Source for Multiview Representation Learning pdf

Ali Jahanian, Phillip Isola, Xavier Puig, 2021, ArXiv.

Culturally-Grounded Analysis of Everyday Creativity in Social Media: A Case Study in Qatari Context

Haewoon Kwak, D. Fox Harrell, Ali Jahanian, 2017, Creativity & Cognition.