Amitabha Sinha

发表

A new algorithm for computing triple-base number system

Subhashis Maitra, Amitabha Sinha, 2012, CARN.

FPGA based implementation of FDCT using Distributed Arithmetic

Amitabha Sinha, Debashis Chowdhury, Swapan Kumar. Samaddar, 2011, 2011 2nd International Conference on Computer and Communication Technology (ICCCT-2011).

High speed residue number system (RNS) based FIR filter using distributed arithmetic (DA)

Amitabha Sinha, Malay Das, Nishant Kumar Giri, 2012, CARN.

A novel architecture for conversion of binary to single digit double base numbers

Amitabha Sinha, Manideepa Mukherjee, A. Sinha, 2010, CARN.

A realistic model for runtime incremental task scheduling in distributed memory multiprocessor systems

Amitabha Sinha, Subhasis Mallick, Amitabh Sinha, 2010, 2010 First International Conference On Parallel, Distributed and Grid Computing (PDGC 2010).

A new architecture for FPGA implementation of a MAC unit for digital signal processors using mixed number system

Amitabha Sinha, Aniruddha Ghosh, Satrughna Singha, 2012, CARN.

Design and implementation of high speed digital multi-programme system based on ITU-T J.83 annexures A and C

Amitabha Sinha, Pratik Kumar Sinha, Pijush Biswas, 2015, 2015 IEEE International Conference on Signal Processing, Informatics, Communication and Energy Systems (SPICES).

A novel architecture of a reconfigurable radio processor for implementing different modulation schemes

Amitabha Sinha, Amiya Karmakar, 2011, 2011 3rd International Conference on Computer Research and Development.

Performance analysis of different DSP algorithms on advanced microcontroller and FPGA

Amitabha Sinha, Sharbari Banerjee, 2009, 2009 International Conference on Advances in Computational Tools for Engineering Applications.

Performance analysis of a FPGA based novel binary and DBNS multiplier

Amitabha Sinha, Amrita Saha, Manideepa Mukherjee, 2013, CARN.

Design and simulation of MAC unit using combinational circuit and adder

Subhashis Maitra, Amitabha Sinha, A. Sinha, 2013, CARN.

A Scheme for Improving Bit Efficiency for Residue Number System

Partha Garai, Chaitali Biswas Dutta, Amitabha Sinha, 2012, ACITY.

Design of High Performance Multiplier Unit using SDTBNS for DSP Applications

Subhashis Maitra, Amitabha Sinha, 2012 .

Generalized architecture for Modulation and Demodulation Techniques

Amitabha Sinha, Swapan Kumar Samaddar, Atri Sanyal, 2013 .

A reconfigurable Digital Signal Processor using residue number system

Amitabha Sinha, Sharbari Banerjee, 2010, 10th International Conference on Information Science, Signal Processing and their Applications (ISSPA 2010).

Performance Analysis of 4 FDCT Algorithms Using Hardware Synthesis and Simulation

Amitabha Sinha, Atri Sanyal, Saloni Kumari, 2018 .

Performance Analysis of FPGA Based MAC Unit using DBTNS Multiplier & TRNS Adder for Signal Processing Algorithm

Amitabha Sinha, Aniruddha Ghosh, 2018 .

On the Design of a Reconfigurable Radio Processor Using FPGA

Amitabha Sinha, Amrita Saha, Amiya Karmakar, 2014 .

A Reconfigurable Architecture to Implement Linear Transforms of Image Processing Applications

Amitabha Sinha, Atri Sanyal, 2021 .

Re-configurable DSP Processor - A New Computing Platform for Software Radio Applications

Amitabha Sinha, Amrita Saha, 2013, 2013 Fourth World Congress on Software Engineering.

An integrated development platform of a reconfigurable radio processor for software defined radio

Amitabha Sinha, Amrita Saha, Pijush Biswas, 2013, CARN.

A Novel Architecture ofMixed Number System MAC Unitfor Digital Signal Processors

Amitabha Sinha, Aniruddha Ghosh, Satrughna Singha, 2010 .

Comparative performance analysis of FPGA-based MAC unit using non-conventional number system in TVL domain for signal processing algorithm

Amitabha Sinha, Aniruddha Ghosh, 2020 .

Field Programmable DSP Arrays - A Novel Reconfigurable Architecture for Efficient Realization of Digital Signal Processing Functions

Amitabha Sinha, Suranjan Chakraborty, Soumojit Acharyya, 2013, 1305.3251.

A novel reconfigurable architecture of a DSP processor for efficient mapping of DSP functions using field programmable DSP arrays pdf

Amitabha Sinha, Suranjan Chakraborty, Soumojit Acharyya, 2013, CARN.

High performance MAC unit for DSP and cryptographic applications

Subhashis Maitra, Amitabha Sinha, 2013, CARN.

A new architecture for FPGA based implementation of conversion of binary to double base number system (DBNS) using parallel search technique

Amitabha Sinha, Aniruddha Ghosh, Satrughna Singha, 2012, CARN.

Design Of A Reconfigurable DSP Processor With Bit Efficient Residue Number System pdf

Partha Garai, Chaitali Biswas Dutta, Amitabha Sinha, 2012, VLSIC 2012.

High efficiency MAC unit used in digital signal processing and elliptic curve cryptography

Subhashis Maitra, Amitabha Sinha, 2013, CARN.

An FPGA Based Architecture of a Novel Reconfigurable Radio Processor for Software Defined Radio

Amitabha Sinha, Amrita Saha, Amrita Saha, 2009, 2009 International Conference on Education Technology and Computer.

FPGA implementation of a novel DCT architecture reducing constant cosine terms

Santanu Pal, Amitabha Sinha, Pijush Biswas, 2013, CARN.

Conversion of binary to single-term triple base numbers for DSP applications

Amitabha Sinha, Anindita Chakraborty, 2012, CARN.

New Algorithm to Convert any Integer in TBNS

Subhashis Maitra, Amitabha Sinha, A. Sinha, 2012 .

FPGA Implementation of MAC Unit for Double Base Ternary Number System (DBTNS) and its Performance Analysis

Amitabha Sinha, Aniruddha Ghosh, 2018 .

High Performance Adaptive Sigma Delta Modulator Design (using LMS Algorithm) for Performance Enhancement of DSP Processors and FPGA Synthesis of the Proposed Architecture

Amitabha Sinha, Amiya Karmakar, Deepshikha Mullick, 2014 .

Field Programmable DSP Arrays - A pdf

Amitabha Sinha, Suranjan Chakraborty, Soumojit Acharyya, 2013, ArXiv.

FPGA implementation of a novel architecture for performance enhancement of Radix-2 FFT

Amitabha Sinha, Nishant Kumar Giri, A. Sinha, 2012, CARN.

FPGA Implementation of RNS Adder Based MAC Unit in Ternary Value Logic Domain for Signal Processing Algorithm and its Performance Analysis

Amitabha Sinha, Aniruddha Ghosh, 2018, 2018 IEEE Electron Devices Kolkata Conference (EDKCON).

Triple-Base Hybrid Joint Sparse Form and its Applications

Subhashis Maitra, Amitabha Sinha, A. Sinha, 2012 .

"Floating point RNS": a new concept for designing the MAC unit of digital signal processor

Amitabha Sinha, Aniruddha Ghosh, Satrughna Singha, 2012, CARN.

A Novel Architecture of Area Efficient FFT Algorithm for FPGA Implementation

Amitabha Sinha, Atin Mukherjee, Debesh Choudhury, 2014, CARN.

A Novel Architecture of Control System Processor Using Field Programmable Gate Array

Amitabha Sinha, Arindam Biswas, 2021 .

Implementation of a Reconfigurable Architecture to Compute Linear Transformations Used in Signal/Image Processing

Amitabha Sinha, Atri Sanyal, 2021, Advances in Intelligent Systems and Computing.

A New Architecture for Transformation of Binary to Double Base Number System (DBNS) with Bases 2 and 5 using Different Search Algorithms

Amitabha Sinha, Satrughna Singha, 2021 .