Dimitrios Karayiannis

ATPD: an automatic test pattern generator for path delay faults

Spyros Tragoudas, Dimitrios Karayiannis, 1996, Proceedings International Test Conference 1996. Test and Design Validity.

Clustering Network Modules with Different Implementations for Delay Minimization

Spyros Tragoudas, Dimitrios Karayiannis, S. Tragoudas, 1998, VLSI Design.

A nonenumerative ATPG for functionally sensitizable path delay faults

Spyros Tragoudas, Dimitrios Karayiannis, 1998, Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231).

Improved nonenumerative path-delay fault-coverage estimation based on optimal polynomial-time algorithms

Spyros Tragoudas, Dimitrios Kagaris, Dimitrios Karayiannis, 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Nonenumerative path delay fault coverage estimation with optimal algorithms

Spyros Tragoudas, Dimitrios Kagaris, Dimitrios Karayiannis, 1997, Proceedings International Conference on Computer Design VLSI in Computers and Processors.

A fast nonenumerative automatic test pattern generator for pathdelay faults

Spyros Tragoudas, Dimitrios Karayiannis, 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Timing-Driven Circuit Implementation

Spyros Tragoudas, Dimitrios Karayiannis, 1998, VLSI Design.

Uniform area timing-driven circuit implementation

Spyros Tragoudas, Dimitrios Karayiannis, 1995, Proceedings. Fifth Great Lakes Symposium on VLSI.

Implementing and clustering modules with complex delays

Spyros Tragoudas, Dimitrios Karayiannis, S. Tragoudas, 1997, Integr..

Delay considerations in testing and synthesis of integrated circuits

Spyros Tragoudas, Dimitrios Karayiannis, 1996 .