Yu-Kai Chou

A 1V 11b 200MS/s Pipelined ADC with Digital Background Calibration in 65nm CMOS

Ya-Lun Yang, Kang-Wei Hsueh, Yu-Kai Chou, 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

A 20-Gb/s half-rate 4:1 multiplexer with multiphase clock architecture in 40-nm CMOS technology

Lin He, Yao Li, Yu-Kai Chou, 2015, 2015 Asia-Pacific Microwave Conference (APMC).

A 288-μW 6-GHz hybrid dynamic comparator with 54-ps delay in 40-nm CMOS

Lin He, Fujiang Lin, Yu-Kai Chou, 2016, 2016 IEEE MTT-S International Wireless Symposium (IWS).

Combo Driver Applications

Ya-Lun Yang, Hsie-Chia Chang, Yu-Kai Chou, 2004 .

A power management unit integrated ADSL/ADSL2+ CPE analog front-end with −93.5dB THD for DMT-based applications

Bo Hu, Yue Feng, Jun Zha, 2014, 2014 IEEE Asian Solid-State Circuits Conference (A-SSCC).

A low-power 10-Gb/s receiver with merged CTLE and DFE summer

Lin He, Fujiang Lin, Yu-Kai Chou, 2016, 2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT).

A CMOS SoC for 56/32/56/16 COMBO driver applications

Ya-Lun Yang, Hsie-Chia Chang, Yu-Kai Chou, 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).