T. Ishijima

and Repair Function

Hiroki Koike, Masahide Takada, Hidenobu Miyamoto, 1990 .

Advanced DMOS Memory Cell using Trench Isolation

S. Kurosawa, M. Takada, T. Ishijima, 1982, 1982 Symposium on VLSI Technology. Digest of Technical Papers.

A capacitor-over-bit-line (COB) cell with a hemispherical-grain storage node for 64 Mb DRAMs

Takamaro Kikkawa, Naoki Kasai, Masato Sakao, 1990, International Technical Digest on Electron Devices.

Self-Test and

Hiroki Koike, Toshio Takeshima, Masahide Takada, 1992 .

A 30-ns 64-Mb DRAM with built-in self-test and self-repair function

Hiroki Koike, Takaho Tanigawa, Hidenobu Miyamoto, 1992 .

A new DRAM cell with a transistor on a lateral epitaxial silicon layer (TOLE cell)

M. Sakao, T. Ishijima, K. Terada, 1990 .

High Speed 4 kbit Static RAM with Silicide Coated Wiring

S. Suzuki, T. Ishijima, Kazukiyo Takahashi, 1981 .

A new VLSI memory cell using capacitance coupling

M. Takada, S. Suzuki, T. Ishijima, 1982, 1982 International Electron Devices Meeting.

A 30 ns 64 Mb DRAM with built-in self-test and repair function

N. Kasai, M. Takada, A. Tanabe, 1992, 1992 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

A new soft-error immune DRAM cell with a transistor on a lateral epitaxial silicon layer (TOLE cell)

M. Sakao, T. Ishijima, K. Terada, 1987, 1987 International Electron Devices Meeting.