Philip M. Chopp

A 1-V 13-mW Single-Path Frequency-Translating $\Delta \Sigma $ Modulator With 55-dB SNDR and 4-MHz Bandwidth at 225 MHz

Anas A. Hamoui, Philip M. Chopp, 2013, IEEE Journal of Solid-State Circuits.

Discrete-Time Modeling of Clock Jitter in Continuous-Time Delta Sigma Modulators.

Anas A. Hamoui, Philip M. Chopp, 2007 .

Design Constraints for Image-Reject Frequency-Translating $\Delta\Sigma$ Modulators

Anas A. Hamoui, Philip M. Chopp, 2009, IEEE Transactions on Circuits and Systems II: Express Briefs.

A 1V 13mW frequency-translating ΔΣ ADC with 55dB SNDR for a 4MHz band at 225MHz

Anas A. Hamoui, Philip M. Chopp, 2011, 2011 IEEE Custom Integrated Circuits Conference (CICC).

Analysis of Clock-Jitter Effects in Continuous-Time $\Delta \Sigma $ Modulators Using Discrete-Time Models

Anas A. Hamoui, Philip M. Chopp, 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.

Design Constraints for Image-Reject Frequency-Translating ΔΣ Modulators

Anas A. Hamoui, Philip M. Chopp, 2009 .

Analysis of Clock-Jitter Effects in Continuous-Time � Modulators Using Discrete-Time Models

Anas A. Hamoui, Philip M. Chopp, 2009 .