J. Juan-Chico

Power and timing modelling, optimisation and simulation

E. Macii, Dimitrios Soudris, J. Juan-Chico, 2005 .

Inertial effect handling method for CMOS digital IC simulation

Antonio J. Acosta, Manuel J. Bellido, Manuel Valencia, 1999 .

Delay degradation effect in submicronic CMOS inverters

Antonio J. Acosta, Manuel J. Bellido, Angel Barriga, 1997 .

Analysis of Metastable Operation in a CMOS Dynamic D-Latch

M. Valencia, J. Juan-Chico, A. J. Acosta, 1997 .

Logical modelling of delay degradation effect in static CMOS gates

Antonio J. Acosta, José L. Huertas, Manuel Valencia, 2000 .

Switching activity evaluation of CMOS digital circuits using logic timing simulation

P. Ruiz-de-Clavijo, Manuel Valencia, C. J. Jiménez, 2001 .