Cyril Chevalier

A Cross-Level Power Estimation Technique to Enhance High-Level Power Models Quality

Arnaud Virazel, Alberto Bosio, Patrick Girard, 2017, J. Low Power Electron..

Distributed asynchronous controllers for clock management in low power systems

Gilles Sicard, Laurent Fesquet, Cyril Chevalier, 2014, 2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS).

A hybrid power modeling approach to enhance high-level power models

Arnaud Virazel, Alberto Bosio, Patrick Girard, 2016, 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS).

HPET: An Efficient Hybrid Power Estimation Technique to Improve High-Level Power Characterization

Arnaud Virazel, Alberto Bosio, Patrick Girard, 2017, J. Circuits Syst. Comput..

A Hybrid Power Estimation Technique to improve IP power models quality

Arnaud Virazel, Alberto Bosio, Patrick Girard, 2016, 2016 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC).

A generic clock controller for low power systems: Experimentation on an AXI bus

Gilles Sicard, Laurent Fesquet, Chouki Aktouf, 2015, 2015 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC).

BIST hardware generator for mixed test scheme

Christian Dufaza, Cyril Chevalier, H. Viallon, 1995, Proceedings the European Design and Test Conference. ED&TC 1995.

LFSROM an algorithm for automatic design synthesis of hardware test pattern generator

Lew Fock Chong Lew Yan Voon, Christian Dufaza, Cyril Chevalier, 1993, Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium.