Bongjin Kim

发表

Low-Complexity Low-Latency Architecture for Matching of Data Encoded With Hard Systematic Error-Correcting Codes

In-Cheol Park, Byeong Yong Kong, Jihyuck Jo, 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A 28Gb/s transceiver with chirp-managed EDC for DML systems

Bongjin Kim, Hyeon-Min Bae, Jaehyeok Yang, 2018, 2018 IEEE International Solid - State Circuits Conference - (ISSCC).

Area-Efficient QC-LDPC Decoder Architecture Based on Stride Scheduling and Memory Bank Division

In-Cheol Park, Bongjin Kim, I. Park, 2013, IEICE Trans. Commun..

Low-Complexity Tree Architecture for Finding the First Two Minima

In-Cheol Park, Bongjin Kim, Youngjoo Lee, 2015, IEEE Transactions on Circuits and Systems II: Express Briefs.

Tail-Overlapped SISO Decoding for High-Throughput LTE-Advanced Turbo Decoders

In-Cheol Park, Bongjin Kim, Injae Yoo, 2014, IEEE Transactions on Circuits and Systems I: Regular Papers.

Two-step beat frequency quantizer based ADC with adaptive reference control for low swing bio-potential signals

Chris H. Kim, Bongjin Kim, Somnath Kundu, 2015, 2015 IEEE Custom Integrated Circuits Conference (CICC).

Reverse Rate Matching for Low-Power LTE-Advanced Turbo Decoders

In-Cheol Park, Bongjin Kim, Injae Yoo, 2015, IEEE Transactions on Circuits and Systems I: Regular Papers.

A 0.2–1.45-GHz Subsampling Fractional- $N$ Digital MDLL With Zero-Offset Aperture PD-Based Spur Cancellation and In Situ Static Phase Offset Detection

Chris H. Kim, Bongjin Kim, Somnath Kundu, 2017, IEEE Journal of Solid-State Circuits.

Immediate Exchange of Extrinsic Information for High-Throughput Turbo Decoding

In-Cheol Park, Bongjin Kim, Injae Yoo, 2012, IEEE Communications Letters.

A fully-digital beat-frequency based ADC achieving 39dB SNDR for a 1.6mVpp input signal

Chris H. Kim, Bongjin Kim, Weichao Xu, 2013, Proceedings of the IEEE 2013 Custom Integrated Circuits Conference.

Real-time Ethernet Network Optimized for Communication between Automotive Electronics

In-Cheol Park, Byeong Yong Kong, Bongjin Kim, 2011 .

Low-Complexity Parallel QPP Interleaver Based on Permutation Patterns

In-Cheol Park, Bongjin Kim, Injae Yoo, 2013, IEEE Trans. Circuits Syst. II Express Briefs.

Automotive ECU Platform using Fault-Tolerant Embedded Processor

In-Cheol Park, Byeong Yong Kong, Bongjin Kim, 2012 .

8-Pipeline-Stage 32-bit Embedded Processor Using Dual Clock Domain

In-Cheol Park, Bongjin Kim, Jinook Song, 2011 .

Snoop-Free Multicore Architecture based on Dual-Core Clusters

Eunchan Kim, In-Cheol Park, Bongjin Kim, 2012 .

A VCO-based ADC employing a multi-phase noise-shaping beat frequency quantizer for direct sampling of Sub-1mV input signals

Chris H. Kim, Bongjin Kim, Somnath Kundu, 2014, Proceedings of the IEEE 2014 Custom Integrated Circuits Conference.

An 8bit, 2.6ps two-step TDC in 65nm CMOS employing a switched ring-oscillator based time amplifier

Chris H. Kim, Bongjin Kim, Hoon Ki Kim, 2015, 2015 IEEE Custom Integrated Circuits Conference (CICC).

True Random Number Generator circuits based on single- and multi-phase beat frequency detection

Keshab K. Parhi, Chris H. Kim, Bongjin Kim, 2014, Proceedings of the IEEE 2014 Custom Integrated Circuits Conference.

A 0.4–1.6GHz spur-free bang-bang digital PLL in 65nm with a D-flip-flop based frequency subtractor circuit

Chris H. Kim, Bongjin Kim, Somnath Kundu, 2015, 2015 Symposium on VLSI Circuits (VLSI Circuits).

Integral transforms, convolution products, and first variations

Bongjin Kim, Byoung Soo Kim, David L. Skoug, 2004, Int. J. Math. Math. Sci..

Optimization of on-chip switched-capacitor DC-DC converters for high-performance applications

Pingqiang Zhou, Sachin S. Sapatnekar, Chris H. Kim, 2012, 2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

All-digital PLL frequency and phase noise degradation measurements using simple on-chip monitoring circuits

Chris H. Kim, Bongjin Kim, Minsu Kim, 2018, 2018 IEEE International Reliability Physics Symposium (IRPS).

Design, Modeling, and Test of a Programmable Adaptive Phase-Shifting PLL for Enhancing Clock Data Compensation

Chris H. Kim, Bongjin Kim, Dong Jiao, 2012, IEEE Journal of Solid-State Circuits.

A 32nm, 0.9V Supply-noise sensitivity tracking PLL for improved clock data compensation featuring a deep trench capacitor based loop filter

Chris H. Kim, Bongjin Kim, Weichao Xu, 2013, 2013 Symposium on VLSI Circuits.

A Supply-Noise Sensitivity Tracking PLL in 32 nm SOI Featuring a Deep Trench Capacitor Based Loop Filter

Chris H. Kim, Bongjin Kim, Weichao Xu, 2014, IEEE Journal of Solid-State Circuits.

Reverse Rate Matching for Low-Power

Bongjin Kim, Injae Yoo, 2015 .

Digital Intensive Circuit Design Techniques for Enhancing Performance of Clock Generators and Data Converters

Bongjin Kim, 2014 .

A 65nm 3.4Gbps HDMI TX PHY with supply-regulated dual-tuning PLL and blending multiplexer

Jaehyun Park, Jongshin Shin, Bongjin Kim, 2008, 2008 IEEE Custom Integrated Circuits Conference.

19.2 A 0.2-to-1.45GHz subsampling fractional-N all-digital MDLL with zero-offset aperture PD-based spur cancellation and in-situ timing mismatch detection

Chris H. Kim, Bongjin Kim, Somnath Kundu, 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

A 870㎒ 0.09㎟ 0.45㎽/㎒ 32b embedded processor using 65㎚ CMOS technology

In-Cheol Park, Bongjin Kim, Youngjoo Lee, 2012 .

Dual-rail decoding of low-density parity-check codes

In-Cheol Park, Bongjin Kim, Hasan Ahmed, 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

QC-LDPC Decoding Architecture based on Stride Scheduling

In-Cheol Park, Bongjin Kim, I. Park, 2011, 2011 IEEE International Symposium of Circuits and Systems (ISCAS).

Memory-Optimized Hybrid Decoding Method for Multi-Rate Turbo Codes

In-Cheol Park, Bongjin Kim, Injae Yoo, 2013, 2013 IEEE 77th Vehicular Technology Conference (VTC Spring).

Colonnade: A Reconfigurable SRAM-Based Digital Bit-Serial Compute-In-Memory Macro for Processing Neural Networks

Bongjin Kim, Taegeun Yoo, Hyunjoon Kim, 2021, IEEE Journal of Solid-State Circuits.

A Reconfigurable 4T2R ReRAM Computing In-Memory Macro for Efficient Edge Applications

Bongjin Kim, Tony Tae-Hyoung Kim, Yuzong Chen, 2021, IEEE Open Journal of Circuits and Systems.

A 252 Spins Scalable CMOS Ising Chip Featuring Sparse and Reconfigurable Spin Interconnects for Combinatorial Optimization Problems

Bongjin Kim, Hyunjoon Kim, Yuqi Su, 2021, 2021 IEEE Custom Integrated Circuits Conference (CICC).

A 32x32 Time-Domain Wavefront Computing Accelerator for Path Planning and Scientific Simulations

Bongjin Kim, Kevin T. C. Chai, Yuqi Su, 2021, 2021 IEEE Custom Integrated Circuits Conference (CICC).

A 20x28 Spins Hybrid In-Memory Annealing Computer Featuring Voltage-Mode Analog Spin Operator for Solving Combinatorial Optimization Problems

Bongjin Kim, Junjie Mu, Yuqi Su, 2021, 2021 Symposium on VLSI Circuits.

A 14-Gb/s clad dielectric waveguide link using 73GHz carrier frequency with a stochastic RF phase synchronization system in 40nm CMOS

Bongjin Kim, Hyeon-Min Bae, Sejun Jeon, 2018, 2018 International Conference on Electronics, Information, and Communication (ICEIC).