H. Numata

Clock-driven on-chip testing for superconductor logic circuits

S. Yorozu, Y. Hashimoto, S. Tahara, 1999, IEEE Transactions on Applied Superconductivity.

System demonstration of a superconducting communication system

S. Nagasawa, S. Yorozu, Y. Hashimoto, 1999, IEEE Transactions on Applied Superconductivity.

Full operation of a three-node pipeline-ring switching chip for a superconducting network system

S. Yorozu, Y. Hashimoto, S. Tahara, 1999, IEEE Transactions on Applied Superconductivity.

A 512kb cross-point cell MRAM

N. Sakimura, S. Miura, S. Tahara, 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

MRAM-writing circuitry to compensate for thermal-variation of magnetization-reversal current

N. Sakimura, S. Miura, S. Tahara, 2002, 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).