J. Valls

Efficient mapping on FPGA of a Viterbi decoder for wireless LANs

T. Sansaloni, F. Angarita, A. Perez-Pascual, 2005, IEEE Workshop on Signal Processing Systems Design and Implementation, 2005..

Reconfigurable video processor for space

Sergio Sáez, J. Valls, L. Armesto Caride, 2020 .

A study about FPGA-based digital filters

T. Sansaloni, J. Valls, M.M. Peiro, 1998, 1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374).

Implementation of a prototypal optical sorter as core of the new pre-treatment configuration of a mechanical-biological treatment plant treating OFMSW through anaerobic digestion

J. Valls, Sergi Astals, M. S. Romero-Güiza, 2014 .

Design and FPGA implementation of digit-serial FIR filters

T. Sansaloni, J. Valls, M.M. Peiro, 1998, 1998 IEEE International Conference on Electronics, Circuits and Systems. Surfing the Waves of Science and Technology (Cat. No.98EX196).