Yoshihito Amemiya

发表

A majority-logic device using an irreversible single-electron box

Tetsuya Asai, Takahide Oya, Takashi Fukui, 2003 .

Neuromorphic CMOS Circuits implementing a Novel Neural Segmentation Model based on Symmetric STDP Learning

Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya, 2007, 2007 International Joint Conference on Neural Networks.

High-Fidelity Pulse-Density Modulation with Noisy Neuromorphic Circuits based on Model of Vestibulo-Ocular Reflex

Tetsuya Asai, Yoshihito Amemiya, Akira Utagawa, 2009 .

Neuromorphic CMOS analog circuit exhibiting array-enhanced stochastic resonance Behavior with population heterogeneity

Tetsuya Asai, Yoshihito Amemiya, Tovar Gessyca, 2010, Neuroscience Research.

Single-electron logic device based on the binary decision diagram

Yoshihito Amemiya, Noboru Asahi, Masamichi Akazawa, 1997 .

A 0.6–4.5 GHz inductorless CMOS low noise amplifier with gyrator-C network

Masayuki Ikebe, Eiichi Sano, Yoshihito Amemiya, 2011, 2011 18th IEEE International Conference on Electronics, Circuits, and Systems.

Basic Circuit Design of a Neural Processor: Analog CMOS Implementation of Spiking Neurons and Dynamic Synapses

Tetsuya Asai, Yoshihito Amemiya, Yusuke Kanazawa, 2003, J. Robotics Mechatronics.

A subthreshold MOS neuron circuit based on the Volterra system

Tetsuya Asai, Yoshihito Amemiya, Yusuke Kanazawa, 2003, IEEE Trans. Neural Networks.

A behavioral model of unipolar resistive RAMs and its application to HSPICE integration

Tetsuya Asai, Yoshihito Amemiya, Nobuo Akou, 2010, IEICE Electron. Express.

An analog CMOS central pattern generator for interlimb coordination in quadruped locomotion

Tetsuya Asai, Kazuki Nakada, Yoshihito Amemiya, 2003, IEEE Trans. Neural Networks.

On-chip PVT compensation techniques for low-voltage CMOS digital LSIs

Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya, 2009, 2009 IEEE International Symposium on Circuits and Systems.

Very-high-speed analog neural network LSI implementation using super self-aligned Si bipolar process technology

Yoshihito Amemiya, Shigeki Aisawa, Takao Matsumoto, 1993, Proceedings of 1993 International Conference on Neural Networks (IJCNN-93-Nagoya, Japan).

A vMOS Cellular-Automaton Device for Differential-of-Gaussian Filtering

Masayuki Ikebe, Yoshihito Amemiya, Tatsuhiko Sunayama, 1999 .

A 1-$\mu\hbox{W}$ 600- $\hbox{ppm}/^{\circ}\hbox{C}$ Current Reference Circuit Consisting of Subthreshold CMOS Circuits

Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya, 2010, IEEE Transactions on Circuits and Systems II: Express Briefs.

Biologically-Inspired Locomotion Controller for a Quadruped Walking Robot: Analog IC Implementation of a CPG-Based Controller

Tetsuya Asai, Kazuki Nakada, Yoshihito Amemiya, 2004, J. Robotics Mechatronics.

A pulse-density modulation circuit exhibiting noise shaping with single-electron neurons

Yusuf Leblebici, Tetsuya Asai, Alexandre Schmid, 2009, 2009 International Joint Conference on Neural Networks.

Noise-Induced Synchronization among Sub-RF CMOS Analog Oscillators for Skew-Free Clock Distribution

Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya, 2008, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Temporal-Domain Neural Competition in Analog Integrate-and-Fire Neurochips

Tetsuya Asai, Yoshihito Amemiya, Yusuke Kanazawa, 2002 .

Temperature-compensated CMOS current reference circuit for ultralow-power subthreshold LSIs

Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya, 2008, IEICE Electron. Express.

A MOS circuit for bursting neural oscillators with excitable oregonators

Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya, 2004, IEICE Electron. Express.

Analog CMOS implementation of a neuromorphic oscillator with current-mode low-pass filters

Tetsuya Asai, Kazuki Nakada, Yoshihito Amemiya, 2005, 2005 IEEE International Symposium on Circuits and Systems.

Floating millivolt reference for PTAT current generation in Subthreshold MOS LSIs

Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya, 2007, 2007 IEEE International Symposium on Circuits and Systems.

Single-electron circuit for inhibitory spiking neural network with fault-tolerant architecture

Yusuf Leblebici, Tetsuya Asai, Alexandre Schmid, 2005, 2005 IEEE International Symposium on Circuits and Systems.

A quadrilateral-object composer for binary images with reaction-diffusion cellular automata

Tetsuya Asai, Masayuki Ikebe, Tetsuya Hirose, 2004 .

Circuit Systems Using Quantum-Effect Devices

Yoshihito Amemiya, 1998 .

Array-Enhanced Stochastic Resonance in a Network of Noisy Neuromorphic Circuits

Tetsuya Asai, Yoshihito Amemiya, Gessyca Maria Tovar, 2010, ICONIP.

Reaction-Diffusion Systems Consisting of Single-Electron Oscillators

Tetsuya Asai, Takahide Oya, Takashi Fukui, 2005, Int. J. Unconv. Comput..

Ultralow-Power Current Reference Circuit with Low Temperature Dependence

Tetsuya Asai, Toshimasa Matsuoka, Kenji Taniguchi, 2005, IEICE Trans. Electron..

Design methodologies for compact logic circuits based on collision-based computing

Tetsuya Asai, Yoshihito Amemiya, Ikuko N. Motoike, 2006, IEICE Electron. Express.

An analog-digital hybrid CMOS circuit for two-dimensional motion detection with correlation neural networks

Tetsuya Asai, Yoshihito Amemiya, Masato Koutani, 2000, Proceedings of the IEEE-INNS-ENNS International Joint Conference on Neural Networks. IJCNN 2000. Neural Computing: New Challenges and Perspectives for the New Millennium.

Temperature-to-frequency converter consisting of subthreshold mosfet circuits for smart temperature-sensor LSIs

Tetsuya Asai, Yoshihito Amemiya, Ken Ueno, 2009, TRANSDUCERS 2009 - 2009 International Solid-State Sensors, Actuators and Microsystems Conference.

A Competitive Neural Network with Neuromorphic Single-Electron Circuits

Tetsuya Asai, Tetsuya Hirose, Takahide Oya, 2003 .

Low-power clock reference circuit for intermittent operation of subthreshold LSIs

Tetsuya Asai, Yoshihito Amemiya, Ken Ueno, 2009, 2009 IEEE International Symposium on Circuits and Systems.

Precisely-timed synchronization among spiking neural circuits on analog VLSIs

Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya, 2006 .

A MOS circuit for depressing synapse and its application to contrast-invariant pattern classification and synchrony detection

Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya, 2004 .

High-fidelity pulse density modulation in neuromorphic electric circuits utilizing natural heterogeneity

Tetsuya Asai, Yoshihito Amemiya, Akira Utagawa, 2011 .

Spiking neuron devices consisting of single-flux-quantum circuits

Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya, 2006 .

Analog CMOS Circuits Implementing Neural Segmentation Model Based on Symmetric STDP Learning

Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya, 2007, ICONIP.

An analog CMOS chip implementing a CNN-based locomotion controller for quadruped walking robots

Tetsuya Asai, Kazuki Nakada, Yoshihito Amemiya, 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

Single-Electron Logic Systems Based on a Graphical Representation of Digital Functions

Yoshihito Amemiya, Y. Amemiya, 2006, IEICE Trans. Electron..

Pulsed Neural Networks Consisting of Single-Flux-Quantum Spiking Neurons

Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya, 2007 .

Low-Voltage Process-Compensated VCO with On-Chip Process Monitoring and Body-Biasing Circuit Techniques

Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya, 2009, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A subthreshold Analog MOS Circuit for Lotka-volterra Chaotic oscillator

Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya, 2006, Int. J. Bifurc. Chaos.

Process Compensation Techniques for Low-Voltage CMOS Digital Circuits

Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya, 2009 .

Eliciting the Potential Functions of Single-Electron Circuits

Yoshihito Amemiya, Masamichi Akazawa, Y. Amemiya, 1997 .

Analog Reaction-Diffusion Chip Imitating Belousov-Zhabotinsky Reaction with Hardware Oregonator Model

Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya, 2005, Int. J. Unconv. Comput..

Analog computation using quantum-flux parametron devices

Tetsuya Asai, Yoshihito Amemiya, Takashi Yamada, 2001 .

An On-Chip PVT Compensation Technique with Current Monitoring Circuit for Low-Voltage CMOS Digital LSIs

Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya, 2010, IEICE Trans. Electron..

Neuro-morphic Circuit Architectures Employing Temporal Noises and Device Fluctuations to Improve Signal-to-noise Ratio in a Single-electron Pulse-density Modulator

Tetsuya Asai, Yoshihito Amemiya, Andrew Kilinga Kikombo, 2011, Int. J. Unconv. Comput..

Threshold-Logic Devices Consisting of Subthreshold CMOS Circuits

Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya, 2009, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A Highly Sensitive Thermosensing CMOS Circuit Based on Self-Biasing Circuit Technique

Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya, 2009 .

A Single-Electron Reaction-Diffusion Device for Computation of a Voronoi Diagram

Tetsuya Asai, Takahide Oya, Yoshihito Amemiya, 2007, Int. J. Unconv. Comput..

A CMOS Reaction-diffusion Device Using Minority-Carrier Diffusion in Semiconductors

Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya, 2007, Int. J. Bifurc. Chaos.

Low-power wake-up receiver with subthreshold CMOS circuits for wireless sensor networks

Masayuki Ikebe, Eiichi Sano, Yoshihito Amemiya, 2013 .

High-Resistance Resistor Consisting of a Subthreshold CMOS Differential Pair

Tetsuya Asai, Yoshihito Amemiya, Ken Ueno, 2010, IEICE Trans. Electron..

Single-flux-quantum circuits for spiking neuron devices

Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya, 2006 .

Stochastic resonance among single-electron neurons on Schottky wrap-gate device

Tetsuya Asai, Seiya Kasai, Takahide Oya, 2006 .

A MOS circuit for depressing synapse and its application to contrast-invariant pattern classification and synchrony detection

Tetsuya Asai, Masayuki Ikebe, Yoshihito Amemiya, 2004, 2004 IEEE International Joint Conference on Neural Networks (IEEE Cat. No.04CH37541).

Stochastic Resonance in an Array of Locally-Coupled McCulloch-Pitts Neurons with Population Heterogeneity

Tetsuya Asai, Yoshihito Amemiya, Akira Utagawa, 2009, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A subthreshold CMOS circuit for a piecewise linear neuromorphic oscillator with current-mode low-pass filters

Tetsuya Asai, Tetsuya Hirose, Kazuki Nakada, 2007, Neurocomputing.

Noise-Induced Phase Synchronization among Nonidentical Analog CMOS Oscillators

Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya, 2008 .

A-1-15 Effects of MOSFET threshold voltage on operation of subthreshold CMOS logic circuits

Tetsuya Asai, Yoshihito Amemiya, Ken Ueno, 2008 .

A νMOS Vision Chip Based on Cellular-Automaton Processing

Tetsuya Asai, Masayuki Ikebe, Yoshihito Amemiya, 2001 .

Neural-processing type optical wavelength demultiplexer using high-speed analog-neural-network integrated circuits

Atsushi Iwata, Yoshihito Amemiya, Akio Sugita, 1991 .

A-1-12 Low-voltage Operation of Master-Slave Flip-Flops

Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya, 2007 .

Reaction-diffusion chip implementing excitable lattices with multiple-valued cellular automata

Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya, 2004, IEICE Electron. Express.

Analog integrate-and-fire neurochips: neural competition in frequency and time domains

Tetsuya Asai, Yoshihito Amemiya, H. Hayashi, 2002, Proceedings of the 5th Biannual World Automation Congress.

Exploiting Temporal Noises and Device Fluctuations in Enhancing Fidelity of Pulse-Density Modulator Consisting of Single-Electron Neural Circuits

Tetsuya Asai, Yoshihito Amemiya, Andrew Kilinga Kikombo, 2009, ICONIP.

Very-High-Speed Analog Neural Network LSI Using Super Self-Aligned Si Bipolar Process Technology

Yoshihito Amemiya, Kazuhiro Noguchi, Shigeki Aisawa, 1994 .

An Inhibitory Neural-Network Circuit Exhibiting Noise Shaping with Subthreshold MOS Neuron Circuits

Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya, 2007, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Pulse-Density Modulation with an Ensemble of Single-Electron Circuits Employing Neuronal Heterogeneity to Achieve High Temporal Resolution

Tetsuya Asai, Yoshihito Amemiya, Andrew Kilinga Kikombo, 2009, NanoNet.

Design of an Artificial Central Pattern Generator with Feedback Controller

Tetsuya Asai, Kazuki Nakada, Yoshihito Amemiya, 2004, Intell. Autom. Soft Comput..

Preface to Special Issue on Micromachire Technologies

Yoshihito Amemiya, Y. Amemiya, 1992 .

A 30-MHz, 90-ppm/°C fully-integrated clock reference generator with frequency-locked loop

Tetsuya Asai, Yoshihito Amemiya, Ken Ueno, 2009, 2009 Proceedings of ESSCIRC.

Discrete Dynamical Systems Consisting of Single-electron Circuits

Tetsuya Asai, Takahide Oya, Yoshihito Amemiya, 2007, Int. J. Bifurc. Chaos.

On the fault tolerance of a clustered single-electron neural network for differential enhancement

Yusuf Leblebici, Tetsuya Asai, Alexandre Schmid, 2005, IEICE Electron. Express.

Binary-decision-diagram device

Yoshihito Amemiya, Noboru Asahi, Masamichi Akazawa, 1995 .

Biomorphic analog devices based on reaction-diffusion systems

Tetsuya Asai, Yoshihito Amemiya, Y. Amemiya, 2003, 33rd International Symposium on Multiple-Valued Logic, 2003. Proceedings..

Neuronal synchrony detection on single-electron neural networks

Tetsuya Asai, Tetsuya Hirose, Takahide Oya, 2006 .

Stochastic Resonance in Retinomorphic Neural Networks with Nonidentical Photoreceptors and Noisy McCulloch-Pitts Neurons

Tetsuya Asai, Yoshihito Amemiya, Akira Utagawa, 2008 .

On-chip power supply for subthreshold-operated CMOS LSIs

Yoshihito Amemiya, Ken Ueno, Hideto Shimada, 2010 .

A 300 nW, 7 ppm/degreeC CMOS voltage reference circuit based on subthreshold MOSFETs

Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya, 2009, ASP-DAC.

On Digital LSI Circuits Exploiting Collision-Based Fusion Gates

Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya, 2008, Int. J. Unconv. Comput..

Offset cancellation with subthreshold-operated feedback circuit for fully differential amplifiers

Tetsuya Asai, Eiichi Sano, Yoshihito Amemiya, 2009, 2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009).

Low Voltage Operation of Master-Slave Flip-Flops for Ultra-Low Power Subthreshold LSIs

Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya, 2008 .

Power-supply circuits for ultralow-power subthreshold MOS-LSIs

Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya, 2006, IEICE Electron. Express.

/spl nu/-MOS cellular-automaton devices for intelligent image sensors

Masayuki Ikebe, Yoshihito Amemiya, Masamichi Akazawa, 1998, 1998 Second International Conference. Knowledge-Based Intelligent Electronic Systems. Proceedings KES'98 (Cat. No.98EX111).

A CMOS Frequency Comparator based on Jamming Avoidance Response of Eigenmannia

Tetsuya Asai, Yoshihito Amemiya, Daichi Fujita, 2009 .

A quadrilateral-object composer for binary images with reaction-diffusion cellular automata

Tetsuya Asai, Masayuki Ikebe, Tetsuya Hirose, 2004, Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits.

Noise-Tolerant Analog Circuits for Sensory Segmentation Based on Symmetric STDP Learning

Tetsuya Asai, Yoshihito Amemiya, Gessyca Maria Tovar, 2008, ICONIP.

A CMOS Watchdog Sensor for Certifying the Quality of Various Perishables with a Wider Activation Energy

Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya, 2006, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A CMOS Phase-Shift oscillator Based on the conduction of Heat

Tetsuya Asai, Yoshihito Amemiya, Takaaki Hirai, 2010, J. Circuits Syst. Comput..

Life Dynamics and Next Generation LSI Device.

Yoshihito Amemiya, Y. Amemiya, 2003 .