P.G. Fernandez

A new RNS architecture for the computation of the scaled 2D-DCT on field-programmable logic

A. Lloris, L. Parrilla, P.G. Fernandez, 2000, Conference Record of the Thirty-Fourth Asilomar Conference on Signals, Systems and Computers (Cat. No.00CH37154).

Fast RNS-based 2D-DCT computation on field-programmable devices

A. Lloris, P.G. Fernandez, J. Ramirez, 2000, 2000 IEEE Workshop on SiGNAL PROCESSING SYSTEMS. SiPS 2000. Design and Implementation (Cat. No.00TH8528).

Implementation of RNS analysis and synthesis filter banks for the orthogonal discrete wavelet transform over FPL devices

A. Lloris, P.G. Fernandez, J. Ramirez, 2000, Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144).

A novel RNS-based SIMD RISC processor for digital signal processing

A. Lloris, J. Ramirez, L. Parrilla, 1999, Conference Record of the Thirty-Third Asilomar Conference on Signals, Systems, and Computers (Cat. No.CH37020).

Implementation of canonical and retimed RNS architectures for the orthogonal 1-D DWT over FPL devices

A. Lloris, J. Ramirez, L. Parrilla, 2000, Conference Record of the Thirty-Fourth Asilomar Conference on Signals, Systems and Computers (Cat. No.00CH37154).

A RNS-based matrix-vector-multiply FCT architecture for DCT computation

A. Lloris, P.G. Fernandez, J. Ramirez, 2000, Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144).

Index-based RNS DWT architectures for custom IC designs

F. Taylor, U. Meyer-Base, J. Ramirez, 2001, 2001 IEEE Workshop on Signal Processing Systems. SiPS 2001. Design and Implementation (Cat. No.01TH8578).

A new implementation of the discrete cosine transform in the residue number system

A. Lloris, L. Parrilla, P.G. Fernandez, 1999, Conference Record of the Thirty-Third Asilomar Conference on Signals, Systems, and Computers (Cat. No.CH37020).