Srivaths Ravi

发表

Variability-Tolerant Register-Transfer Level Synthesis

Anish Muttreja, Srivaths Ravi, Niraj K. Jha, 2008, 21st International Conference on VLSI Design (VLSID 2008).

Transient power management through high level synthesis

Srivaths Ravi, Ganesh Lakshminarayana, Anand Raghunathan, 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).

Embedding security in wireless embedded systems

Srivaths Ravi, Anand Raghunathan, Srimat T. Chakradhar, 2003, 16th International Conference on VLSI Design, 2003. Proceedings..

Quantile – Quantile Fitting Approach to Detect Site to Site Variations in Massive Multi-site Testing

Srivaths Ravi, Praise O. Farayola, Shravan K. Chaganti, 2020, 2020 IEEE 38th VLSI Test Symposium (VTS).

Tutorial T2: Validation and Debug of Security and Trust Issues in Embedded Systems

Srivaths Ravi, Swarup Bhunia, Prabhat Mishra, 2015, 2015 28th International Conference on VLSI Design.

Configuration and Extension of Embedded Processors to Optimize IPSec Protocol Execution

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Generation of distributed logic-memory architectures through high-level synthesis

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Tutorial T9: Designing Secure SoCs

Srivaths Ravi, Stefan Mangard, 2013, 2013 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems.

Hardware accelerated power estimation

Srivaths Ravi, Anand Raghunathan, Joel Coburn, 2005, Design, Automation and Test in Europe.

High-level test compaction techniques

Srivaths Ravi, Niraj K. Jha, Ganesh Lakshminarayana, 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Fault-diagnosis-based technique for establishing RTL and gate-levelcorrespondences

Srivaths Ravi, Niraj K. Jha, Vamsi Boppana, 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Tamper resistance mechanisms for secure embedded systems

Srivaths Ravi, Anand Raghunathan, Srimat T. Chakradhar, 2004, 17th International Conference on VLSI Design. Proceedings..

Special Session: Security on SoC

Srivaths Ravi, Hiroto Yasuura, Catherine H. Gebotys, 2002, ISSS.

Methodology for early and accurate test power estimation at RTL

Srivaths Ravi, Abhay Singh, Milan Shetty, 2010, 2010 IEEE International Test Conference.

A Framework for Extensible Processor Based MPSoC Design

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2007 .

Test-Volume Reduction in Systems-on-a-Chip Using Heterogeneous and Multilevel Compression Techniques

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Generation of Heterogeneous Distributed Architectures for Memory-Intensive Applications Through High-Level Synthesis

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

TAO: regular expression-based register-transfer level testability analysis and optimization

Srivaths Ravi, Niraj K. Jha, Ganesh Lakshminarayana, 2001, IEEE Trans. Very Large Scale Integr. Syst..

Multi-CoDec Configurations for Low Power and High Quality Scan Test

Srivaths Ravi, Rubin A. Parekhji, Arvind Jain, 2011, 2011 24th Internatioal Conference on VLSI Design.

Reducing test application time in high-level test generation

Srivaths Ravi, Niraj K. Jha, Ganesh Lakshminarayana, 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

On automatic generation of RTL validation test benches using circuit testing techniques

Srivaths Ravi, Indradeep Ghosh, 2003, GLSVLSI '03.

Systematic Software-Based Self-Test for Pipelined Processors

Srivaths Ravi, Anand Raghunathan, Mihalis Psarakis, 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Securing mobile appliances: new challenges for the system designer

Srivaths Ravi, Anand Raghunathan, Jean-Jacques Quisquater, 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

A Scalable Application-Specific Processor Synthesis Methodology

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2003, ICCAD 2003.

Power emulation: a new paradigm for power estimation

Srivaths Ravi, Anand Raghunathan, Joel Coburn, 2005, Proceedings. 42nd Design Automation Conference, 2005..

Power estimation for cycle-accurate functional descriptions of hardware

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..

A Synthesis Methodology for Hybrid Custom Instruction and Coprocessor Generation for Extensible Processors

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Satisfiability-based test generation for nonseparable RTL controller-datapath circuits

Srivaths Ravi, Niraj K. Jha, Loganathan Lingappan, 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A framework for testing core-based systems-on-a-chip

Srivaths Ravi, Niraj K. Jha, Ganesh Lakshminarayana, 1999, 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051).

Energy and execution time analysis of a software-based trusted platform module

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2007 .

Efficient fingerprint-based user authentication for embedded systems

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2005, Proceedings. 42nd Design Automation Conference, 2005..

A scalable application-specific processor synthesis methodology

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2003, ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486).

Active Learning Driven Data Acquisition for Sensor Networks

Anish Muttreja, Srivaths Ravi, Niraj K. Jha, 2006, 11th IEEE Symposium on Computers and Communications (ISCC'06).

SECA: security-enhanced communication architecture

Srivaths Ravi, Anand Raghunathan, Srimat T. Chakradhar, 2005, CASES '05.

Heterogeneous and multi-level compression techniques for test volume reduction in systems-on-chip

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2005, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design.

Architectural support for safe software execution on embedded processors

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2006, Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06).

High-level synthesis using computation-unit integrated memories

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2004, ICCAD 2004.

Systematic Software-Based Self-Test for Pipelined Processors

Michail Maniatakos, Srivaths Ravi, Anand Raghunathan, 2008, IEEE Trans. Very Large Scale Integr. Syst..

Impact of configurability and extensibility on IPSec protocol execution on embedded processors

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2006, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06).

Exploring Software Partitions for Fast Security Processing on a Multiprocessor Mobile SoC

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A scalable software-based self-test methodology for programmable processors

Sujit Dey, Li Chen, Srivaths Ravi, 2003, DAC '03.

TAO-BIST: a framework for testability analysis and optimization of RTL circuits for BIST

Srivaths Ravi, Niraj K. Jha, Ganesh Lakshminarayana, 1999, Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146).

Energy and Execution Time Analysis of a Software-based Trusted Platform Module

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

Security as a new dimension in embedded system design

Srivaths Ravi, Anand Raghunathan, Ruby B. Lee, 2004, Proceedings. 41st Design Automation Conference, 2004..

High-level synthesis using computation-unit integrated memories

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..

Hybrid Simulation for Energy Estimation of Embedded Software

Anish Muttreja, Srivaths Ravi, Niraj K. Jha, 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Test generation for non-separable RTL controller-datapath circuits using a satisfiability based approach

Srivaths Ravi, Niraj K. Jha, Loganathan Lingappan, 2003, Proceedings 21st International Conference on Computer Design.

Methodology for low power test pattern generation using activity threshold control logic

Srivaths Ravi, V. R. Devanathan, Rubin A. Parekhji, 2007, ICCAD 2007.

An integrated SCR and TVR Technique for shift power reduction on Linear and Double-Tree Scan architectures

Srivaths Ravi, George Kurien, Narayana Rao Vv, 2009 .

Secure embedded processing through hardware-assisted run-time monitoring

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2005, Design, Automation and Test in Europe.

Controller Resynthesis for Testability Enhancement of RTL Controller/Data Path Circuits

Sujit Dey, Srivaths Ravi, Indradeep Ghosh, 1998, J. Electron. Test..

RTL-Aware Cycle-Accurate Functional Power Estimation

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A technique for identifying RTL and gate-level correspondences

Srivaths Ravi, Niraj K. Jha, Vamsi Boppana, 2000, Proceedings 2000 International Conference on Computer Design.

Removal of memory access bottlenecks for scheduling control-flow intensive behavioral descriptions

Srivaths Ravi, Niraj K. Jha, Ganesh Lakshminarayana, 1998, 1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287).

High-level synthesis of distributed logic-memory architectures

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2002, ICCAD 2002.

Synthesis of Heterogeneous Distributed Architectures for Memory-Intensive Applications

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2003, ICCAD 2003.

A Regression Based Technique for ATE-Aware Test Data Volume Estimation of System-on-Chips

Srivaths Ravi, Rajesh Tiwari, Rubin A. Parekhji, 2008, 26th IEEE VLSI Test Symposium (vts 2008).

Securing Wireless Data: System Architecture Challenges

Srivaths Ravi, Anand Raghunathan, Nachiketh R. Potlapally, 2002, ISSS.

Power Analysis and Reduction Techniques for Transition Fault Testing

Srivaths Ravi, Rubin A. Parekhji, Srinivas Kumar Vooka, 2008, 2008 17th Asian Test Symposium.

Aiding Side-Channel Attacks on Cryptographic Software With Satisfiability-Based Analysis

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

High-level synthesis of distributed logic-memory architectures

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2002, IEEE/ACM International Conference on Computer Aided Design, 2002. ICCAD 2002..

Application-specific heterogeneous multiprocessor synthesis using extensible processors

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Synthesis of system-on-a-chip for testability

Srivaths Ravi, Niraj K. Jha, N. Jha, 2001, VLSI Design 2001. Fourteenth International Conference on VLSI Design.

Energy-optimizing source code transformations for OS-driven embedded software

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2004, 17th International Conference on VLSI Design. Proceedings..

Energy estimation for extensible processors

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

Test synthesis of systems-on-a-chip

Srivaths Ravi, Niraj K. Jha, N. Jha, 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Synthesis of Heterogeneous Distributed Architectures for Memory-Intensive Applications

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2003, ICCAD.

Test Power Reduction Using Integrated Scan Cell and Test Vector Reordering Techniques on Linear Scan and Double Tree Scan Architectures

V. Kamakoti, George Kurian, Srivaths Ravi, 2009, J. Low Power Electron..

Secure Embedded Processing through Hardware-assisted

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2005 .

Eliminating memory bottlenecks for a JPEG encoder through distributed logic-memory architecture and computation-unit integrated memory

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2005, Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005..

A study of the energy consumption characteristics of cryptographic algorithms and security protocols

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2006, IEEE Transactions on Mobile Computing.

Methodology for low power test pattern generation using activity threshold control logic

Srivaths Ravi, V. R. Devanathan, Rubin A. Parekhji, 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.

Testing of core-based systems-on-a-chip

Srivaths Ravi, Niraj K. Jha, Ganesh Lakshminarayana, 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Architectural Support for Run-Time Validation of Program Data Properties

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Custom-instruction synthesis for extensible-processor platforms

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Methodology for Early RTL Testability and Coverage Analysis and Its Application to Industrial Designs

Srivaths Ravi, Rajesh Tiwari, Chandan Kumar, 2014, 2014 IEEE 23rd Asian Test Symposium.

Low Power Test for Nanometer System-on-Chips (SoCs)

Srivaths Ravi, Rubin A. Parekhji, Jayashree Saxena, 2008, J. Low Power Electron..

Security in embedded systems: Design challenges

Srivaths Ravi, Anand Raghunathan, Paul C. Kocher, 2004, TECS.

Power estimation for cycle-accurate functional descriptions of hardware

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2004, ICCAD 2004.

Analyzing the energy consumption of security protocols

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2003, ISLPED '03.

System design methodologies for a wireless security processing platform

Srivaths Ravi, Anand Raghunathan, Murugan Sankaradass, 2002, DAC '02.

Software architecture exploration for high-performance security processing on a multiprocessor mobile SoC

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2006, 2006 43rd ACM/IEEE Design Automation Conference.

Synthesis of custom processors based on extensible platforms

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2002, IEEE/ACM International Conference on Computer Aided Design, 2002. ICCAD 2002..

Synthesis of application-specific heterogeneous multiprocessor architectures using extensible processors

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2005, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design.

Fast test generation for circuits with RTL and gate-level views

Srivaths Ravi, Niraj K. Jha, N. Jha, 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

Energy-optimizing source code transformations for operating system-driven embedded software

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2007, TECS.

Controller resynthesis for testability enhancement of RTL controller/data path circuits

Sujit Dey, Srivaths Ravi, Indradeep Ghosh, 1998, Proceedings Eleventh International Conference on VLSI Design.

A hybrid energy-estimation technique for extensible processors

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

TAO-BIST: A framework for testability analysis and optimization forbuilt-in self-test of RTL circuits

Srivaths Ravi, Niraj K. Jha, Ganesh Lakshminarayana, 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Design Techniques with Multiple Scan Compression CoDecs for Low Power and High Quality Scan Test

Srivaths Ravi, Rubin A. Parekhji, Arvind Jain, 2011, J. Low Power Electron..

Automated Energy/Performance Macromodeling of Embedded Software

Anish Muttreja, Srivaths Ravi, Niraj K. Jha, 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Demystifying automotive safety and security for semiconductor developer

Srivaths Ravi, V. Prasanth, David Foley, 2017, 2017 IEEE International Test Conference (ITC).

Efficient RTL power estimation for large designs

Srivaths Ravi, Anand Raghunathan, Srimat T. Chakradhar, 2003, 16th International Conference on VLSI Design, 2003. Proceedings..

Hybrid custom instruction and co-processor synthesis methodology for extensible processors

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2006, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06).

Power-aware test: Challenges and solutions

Srivaths Ravi, S. Ravi, 2007, 2007 IEEE International Test Conference.

A Scalable Synthesis Methodology for Application-Specific Processors

Srivaths Ravi, Niraj K. Jha, Fei Sun, 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Hybrid simulation for embedded software energy estimation

Anish Muttreja, Srivaths Ravi, Niraj K. Jha, 2005, Proceedings. 42nd Design Automation Conference, 2005..

Transport protocol optimization for energy efficient wireless embedded systems

Luca Benini, Srivaths Ravi, Anand Raghunathan, 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

Hybrid Architectures for Efficient and Secure Face Authentication in Embedded Systems

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Optimizing public-key encryption for wireless clients

Srivaths Ravi, Ganesh Lakshminarayana, Anand Raghunathan, 2002, 2002 IEEE International Conference on Communications. Conference Proceedings. ICC 2002 (Cat. No.02CH37333).

Synthesis of custom processors based on extensible platforms

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2002, ICCAD 2002.

TAO: regular expression based high-level testability analysis and optimization

Srivaths Ravi, Niraj K. Jha, Ganesh Lakshminarayana, 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

Integrating variable-latency components into high-level synthesis

Srivaths Ravi, Ganesh Lakshminarayana, Vijay Raghunathan, 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

A generic low power scan chain wrapper for designs using scan compression

Srivaths Ravi, Rajesh Tiwari, Rubin A. Parekhji, 2010, 2010 28th VLSI Test Symposium (VTS).

Architectures for efficient face authentication in embedded systems

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2006, Proceedings of the Design Automation & Test in Europe Conference.

Enhancing security through hardware-assisted run-time validation of program data properties

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2005, 2005 Third IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'05).

Use of Computation-Unit Integrated Memories in High-Level Synthesis

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Satisfiability-based Framework for Enabling Side-channel Attacks on Cryptographic Software

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2006, Proceedings of the Design Automation & Test in Europe Conference.

Hardware-Assisted Run-Time Monitoring for Secure Program Execution on Embedded Processors

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

High-level synthesis with variable-latency components

Srivaths Ravi, Ganesh Lakshminarayana, Vijay Raghunathan, 2000, VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design.

Tutorial T3A: Testing Low-Power Integrated Circuits: Challenges, Solutions, and Industry Practices

Srivaths Ravi, Vivek Chickermane, Krishna Chakravadhanula, 2014, VLSI Design.

Detection of Site to Site Variations From Volume Measurement Data in Multisite Semiconductor Testing

Srivaths Ravi, Degang Chen, Praise O. Farayola, 2021, IEEE Transactions on Instrumentation and Measurement.

An Ordinal Optimization-Based Approach To Die Distribution Estimation For Massive Multi-site Testing Validation: A Case Study

Srivaths Ravi, Degang Chen, Praise O. Farayola, 2021, 2021 IEEE European Test Symposium (ETS).

Massive Multisite Variability-Aware Die Distribution Estimation for Analog/Mixed-Signal Circuits Test Validation

Srivaths Ravi, Degang Chen, Praise O. Farayola, 2021, 2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS).

Trusted Platform based Key Establishment & Management for Sensor Networks

Srivaths Ravi, Anand Raghunathan, Saurabh Ganeriwal, 2006 .