Niraj K. Jha

发表

Variability-Tolerant Register-Transfer Level Synthesis

Anish Muttreja, Srivaths Ravi, Niraj K. Jha, 2008, 21st International Conference on VLSI Design (VLSID 2008).

Common-case computation: a high-level energy and performance optimization technique

Sujit Dey, Niraj K. Jha, Ganesh Lakshminarayana, 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

COSYN: hardware-software co-synthesis of embedded systems

Niraj K. Jha, Ganesh Lakshminarayana, Bharat P. Dave, 1997, DAC.

A framework for defending embedded systems against software attacks

Niraj K. Jha, Anand Raghunathan, Najwa Aaraj, 2011, TECS.

Switching and Finite Automata Theory: Preface

Niraj K. Jha, Zvi Kohavi, 2009 .

Separable codes for detecting unidirectional errors

Niraj K. Jha, 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

A High-level Interconnect Power Model for Design Space Exploration

Niraj K. Jha, Pallav Gupta, Lin Zhong, 2003, ICCAD 2003.

Editorial

Niraj K. Jha, 2007, IEEE Trans. Very Large Scale Integr. Syst..

ALLCN: an automatic logic-to-layout tool for carbon nanotube based nanotechnology

Wei Zhang, Niraj K. Jha, Wei Zhang, 2005, 2005 International Conference on Computer Design.

A Secure User Interface for Web Applications Running Under an Untrusted Operating System

Niraj K. Jha, Anand Raghunathan, Chunxiao Li, 2010, 2010 10th IEEE International Conference on Computer and Information Technology.

Emerging Frontiers in Embedded Security

Meng Zhang, Niraj K. Jha, Anand Raghunathan, 2013, 2013 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems.

Common-case computation: a high-level technique for power and performance optimization

Sujit Dey, Niraj K. Jha, Ganesh Lakshminarayana, 1999, DAC '99.

Ultra-Low-Leakage and High-Performance Logic Circuit Design Using Multiparameter Asymmetric FinFETs

Niraj K. Jha, Sourindra Chaudhuri, 2016, ACM J. Emerg. Technol. Comput. Syst..

Thermal characterization of BIST, scan design and sequential test methodologies

Niraj K. Jha, Muzaffer O. Simsir, 2009, 2009 International Test Conference.

Design and analysis of algorithm-based fault-tolerant systems under the extended graph-theoretic model

Niraj K. Jha, Shalini Yajnik, 1994 .

A Totally Self-Checking Checker for a Parallel Unordered Coding Scheme

Niraj K. Jha, Steven W. Burns, 1994, IEEE Trans. Computers.

Genetic Programming for Energy-Efficient and Energy-Scalable Approximate Feature Computation in Embedded Inference Systems

Hongyang Jia, Naveen Verma, Niraj K. Jha, 2018, IEEE Transactions on Computers.

A comprehensive high-level synthesis system for control-flow intensive behaviors

Li Shang, Niraj K. Jha, Anand Raghunathan, 2003, GLSVLSI '03.

On the design of robust multiple fault testable CMOS combinational logic circuits

Sudhakar M. Reddy, Niraj K. Jha, Sandip Kundu, 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.

Physiological Information Leakage: A New Frontier in Health Information Security

Susmita Sur-Kolay, Niraj K. Jha, Arsalan Mohsen Nia, 2016, IEEE Transactions on Emerging Topics in Computing.

FinFET-based power simulator for interconnection networks

Niraj K. Jha, Chun-Yi Lee, 2008, JETC.

Combined Dynamic Voltage Scaling and Adaptive Body Biasing for Heterogeneous Distributed Real-time Embedded Systems

Niraj K. Jha, Jiong Luo, Le Yan, 2003, ICCAD 2003.

Design space exploration of FinFET cache

Niraj K. Jha, Aoxiang Tang, 2013, JETC.

Resource budgeting for Multiprocess High-level synthesis

Sujit Dey, Niraj K. Jha, Anand Raghunathan, 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Robot Design With Neural Networks, MILP Solvers and Active Learning pdf

Niraj K. Jha, Dana Chee, Brendan Englot, 2020, ArXiv.

Behavioral synthesis for low power

Niraj K. Jha, Anand Raghunathan, N. Jha, 1994, Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors.

Gated-diode FinFET DRAMs: Device and circuit design-considerations

Niraj K. Jha, Ajay N. Bhoj, 2010, JETC.

Design and synthesis of self-checking VLSI circuits

Niraj K. Jha, Sying-Jyan Wang, N. Jha, 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Dynamic power optimization of interactive systems

Niraj K. Jha, Lin Zhong, 2004, 17th International Conference on VLSI Design. Proceedings..

A Totally Self-checking Checker

Niraj K. Jha, 1989 .

Leakage power analysis and reduction during behavioral synthesis

Niraj K. Jha, Kamal S. Khouri, 2002, IEEE Trans. Very Large Scale Integr. Syst..

A totally self-checking checker for Borden's code

Niraj K. Jha, 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Testing of multiple-output domino logic (MODL) CMOS circuits

Niraj K. Jha, Q. Tong, 1990 .

Configuration and Extension of Embedded Processors to Optimize IPSec Protocol Execution

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Generation of distributed logic-memory architectures through high-level synthesis

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Majority and Minority Network Synthesis With Application to QCA-, SET-, and TPL-Based Nanotechnologies

Rui Zhang, Niraj K. Jha, Pallav Gupta, 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

COWLS: hardware-software co-synthesis of distributed wireless low-power embedded client-server systems

Niraj K. Jha, Robert P. Dick, N. Jha, 2000, VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design.

Multiple Stuck-Open Fault Detection in CMOS Logic Circuits

Niraj K. Jha, 1988, IEEE Trans. Computers.

A new transition count method for testing of logic circuits

Niraj K. Jha, Konstantinos I. Diamantaras, 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

High-level test compaction techniques

Srivaths Ravi, Niraj K. Jha, Ganesh Lakshminarayana, 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Fast FinFET Device Simulation under Process-Voltage Variations Using an Assisted Speed-Up Mechanism

Niraj K. Jha, Sourindra Chaudhuri, Ajay N. Bhoj, 2016, 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID).

Fault-diagnosis-based technique for establishing RTL and gate-levelcorrespondences

Srivaths Ravi, Niraj K. Jha, Vamsi Boppana, 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Synthesis of Sequential Circuits for Robust Path Delay Fault Testability

Niraj K. Jha, Sandeep Bhatia, 1993, The Sixth International Conference on VLSI Design.

NeST: A Neural Network Synthesis Tool Based on a Grow-and-Prune Paradigm

Niraj K. Jha, Xiaoliang Dai, Hongxu Yin, 2017, IEEE Transactions on Computers.

High-level software energy macro-modeling

Niraj K. Jha, Ganesh Lakshminarayana, Anand Raghunathan, 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

GenFin: Genetic Algorithm-Based Multiobjective Statistical Logic Circuit Optimization Using Incremental Statistical Analysis

Niraj K. Jha, Aoxiang Tang, N. Jha, 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A hybrid nano-CMOS architecture for defect and fault tolerance

Niraj K. Jha, Martin Rötteler, Srihari Cadambi, 2009, JETC.

Embedded Reconfigurable Augmented DC-DC Boost Converter for Fast Transient Recovery

Niraj K. Jha, Amit Patra, Santanu Kapat, 2013, 2013 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems.

SPRING: A Sparsity-Aware Reduced-Precision Monolithic 3D CNN Accelerator Architecture for Training and Inference pdf

Niraj K. Jha, Ye Yu, N. Jha, 2019, IEEE Transactions on Emerging Topics in Computing.

Synthesis of multi-level combinational circuits for complete robust path delay fault testability

Irith Pomeranz, Sudhakar M. Reddy, Niraj K. Jha, 1992, [1992] Digest of Papers. FTCS-22: The Twenty-Second International Symposium on Fault-Tolerant Computing.

A Hierarchical Inference Model for Internet-of-Things

Niraj K. Jha, Zeyu Wang, Hongxu Yin, 2018, IEEE Transactions on Multi-Scale Computing Systems.

An ILP formulation for low power based on minimizing switched capacitance during data path allocation

Niraj K. Jha, Anand Raghunathan, 1995, Proceedings of ISCAS'95 - International Symposium on Circuits and Systems.

Energy comparison and optimization of wireless body-area network technologies

Niraj K. Jha, Lin Zhong, Le Yan, 2007, BODYNETS.

A Framework for Extensible Processor Based MPSoC Design

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2007 .

Test-Volume Reduction in Systems-on-a-Chip Using Heterogeneous and Multilevel Compression Techniques

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Synthesis of power-optimized and area-optimized circuits from hierarchical behavioral descriptions

Niraj K. Jha, Ganesh Lakshminarayana, 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

Behavioral synthesis for hierarchical testability of controller/data path circuits with conditional branches

Niraj K. Jha, Sandeep Bhatia, 1994, Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors.

MOGAC: a multiobjective genetic algorithm for the co-synthesis of hardware-software embedded systems

Niraj K. Jha, Robert P. Dick, 1997, 1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

CASPER: Concurrent hardware-software co-synthesis of hard real-time aperiodic and periodic specifications of embedded system architectures

Niraj K. Jha, Bharat P. Dave, N. Jha, 1998, Proceedings Design, Automation and Test in Europe.

Editorial Announcing a New Editor-in-Chief

Niraj K. Jha, N. Jha, 2011, IEEE Transactions on Very Large Scale Integration (vlsi) Systems.

Generation of Heterogeneous Distributed Architectures for Memory-Intensive Applications Through High-Level Synthesis

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Reversible logic synthesis with Fredkin and Peres gates

Niraj K. Jha, James Donald, N. Jha, 2008, JETC.

Automated Quantum Circuit Synthesis and Cost Estimation for the Binary Welded Tree Oracle

Niraj K. Jha, Amlan Chakrabarti, Mrityunjay Ghosh, 2017, ACM J. Emerg. Technol. Comput. Syst..

Optimized Quantum Gate Library for Various Physical Machine Descriptions

Niraj K. Jha, Amlan Chakrabarti, Chia-Chun Lin, 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

User-perceived latency driven voltage scaling for interactive applications

Niraj K. Jha, Lin Zhong, Le Yan, 2005, Proceedings. 42nd Design Automation Conference, 2005..

Threshold/majority logic synthesis and concurrent error detection targeting nanoelectronic implementations

Rui Zhang, Niraj K. Jha, N. Jha, 2006, GLSVLSI '06.

Fin Prin: Analysis and Optimization of FinFET Logic Circuits under PVT Variations

Niraj K. Jha, Yang Yang, 2013, 2013 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems.

Wearable Medical Sensor-Based System Design: A Survey

Susmita Sur-Kolay, Niraj K. Jha, Anand Raghunathan, 2017, IEEE Transactions on Multi-Scale Computing Systems.

Architecture-Level Power Estimation

Niraj K. Jha, Anand Raghunathan, Sujit Dey, 1998 .

DISPATCH: Design Space Exploration of Cyber-Physical Systems pdf

Niraj K. Jha, Kenza Hamidouche, Prerit Terway, 2020, ArXiv.

Genesis: a behavioral synthesis system for hierarchical testability

Niraj K. Jha, Sandeep Bhatia, N. Jha, 1994, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.

Partitioned Encoding Schemes for Algorithm-Based Fault Tolerance in Massively Parallel Systems

Niraj K. Jha, Jennifer Rexford, 1994, IEEE Trans. Parallel Distributed Syst..

Smart Healthcare

Niraj K. Jha, Arsalan Mosenia, Hongxu Yin, 2018, Found. Trends Electron. Des. Autom..

Localized Heating for Building Energy Efficiency

Niraj K. Jha, Anand Raghunathan, Chunxiao Li, 2013, 2013 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems.

TAO: regular expression-based register-transfer level testability analysis and optimization

Srivaths Ravi, Niraj K. Jha, Ganesh Lakshminarayana, 2001, IEEE Trans. Very Large Scale Integr. Syst..

Energy efficiency of handheld computer interfaces: limits, characterization and practice

Niraj K. Jha, Lin Zhong, N. Jha, 2005, MobiSys '05.

DISASTER: Dedicated Intelligent Security Attacks on Sensor-Triggered Emergency Responses

Susmita Sur-Kolay, Niraj K. Jha, Anand Raghunathan, 2017, IEEE Transactions on Multi-Scale Computing Systems.

Reducing test application time in high-level test generation

Srivaths Ravi, Niraj K. Jha, Ganesh Lakshminarayana, 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

Comments on 'A MOS implementation of totally self-checking checker for the 1-out-of-3 code'

Niraj K. Jha, 1989 .

Self-checking DCVS circuits

Niraj K. Jha, 1992 .

Power-profile driven variable voltage scaling for heterogeneous distributed real-time embedded systems

Niraj K. Jha, Jiong Luo, 2003, 16th International Conference on VLSI Design, 2003. Proceedings..

Hierarchical test generation and design for testability of ASPPs and ASIPs

Niraj K. Jha, Anand Raghunathan, Indradeep Ghosh, 1997, DAC.

Dynamic Power Optimization Targeting User Delays in Interactive Systems

Niraj K. Jha, Lin Zhong, N. Jha, 2006, IEEE Transactions on Mobile Computing.

Variable-Pipeline-Stage Router

Niraj K. Jha, Chun-Yi Lee, 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Wavesched: a novel scheduling technique for control-flow intensive designs

Niraj K. Jha, Ganesh Lakshminarayana, Kamal S. Khouri, 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Efficient Methodologies for 3-D TCAD Modeling of Emerging Devices and Circuits

Rajiv V. Joshi, Niraj K. Jha, Ajay N. Bhoj, 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

CABA: Continuous Authentication Based on BioAura

Susmita Sur-Kolay, Niraj K. Jha, Anand Raghunathan, 2017, IEEE Transactions on Computers.

Corrections to "mogac: a multiobjective genetic algorithm for hardware-software cosynthesis of distributed embedded systems"

Niraj K. Jha, Robert P. Dick, N. Jha, 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Multiple input bridging fault detection in CMOS sequential circuits

Niraj K. Jha, Sying-Jyan Wang, Phillip C. Gripka, 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.

Improving the Trustworthiness of Medical Device Software with Formal Verification Methods

Niraj K. Jha, Anand Raghunathan, Chunxiao Li, 2013, IEEE Embedded Systems Letters.

Fast Enhancement of Validation Test Sets for Improving the Stuck-at Fault Coverage of RTL Circuits

Niraj K. Jha, Loganathan Lingappan, Vijay Gangaram, 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Analysis and design of a hardware/software trusted platform module for embedded systems

Niraj K. Jha, Anand Raghunathan, Najwa Aaraj, 2008, TECS.

EMSIM: an energy simulation framework for an embedded operating system

Niraj K. Jha, Anand Raghunathan, T. K. Tan, 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

NanoMap: An Integrated Design Optimization Flow for a Hybrid Nanotube/CMOS Dynamically Reconfigurable Architecture

Wei Zhang, Li Shang, Niraj K. Jha, 2007, 2007 44th ACM/IEEE Design Automation Conference.

Efficient diagnosis in algorithm-based fault tolerant multiprocessor systems

Niraj K. Jha, Santhanam Srinivasan, 1993, Proceedings of 1993 IEEE International Conference on Computer Design ICCD'93.

Smart, Secure, Yet Energy-Efficient, Internet-of-Things Sensors

Niraj K. Jha, Ayten Ozge Akmandor, Hongxu YIN, 2018, IEEE Transactions on Multi-Scale Computing Systems.

Integrated functional partitioning and synthesis for low power distributed systems of systems-on-a-chip

Niraj K. Jha, Yunsi Fei, N. Jha, 2005, Int. J. Embed. Syst..

Test Generation for Combinational Quantum Cellular Automata (QCA) Circuits

Niraj K. Jha, Loganathan Lingappan, Pallav Gupta, 2006, Proceedings of the Design Automation & Test in Europe Conference.

Editorial Appointments for the 2009-2010 Term

Niraj K. Jha, 2009, IEEE Trans. Very Large Scale Integr. Syst..

High-level test synthesis: a survey

Niraj K. Jha, Indradeep Ghosh, 1998, Integr..

Nanotechnology in the Service of Embedded and Ubiquitous Computing

Niraj K. Jha, 2005, EUC.

An energy-aware framework for coordinated dynamic software management in mobile computers

Niraj K. Jha, Lin Zhong, Yunsi Fei, 2004, The IEEE Computer Society's 12th Annual International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunications Systems, 2004. (MASCOTS 2004). Proceedings..

High-level power modeling of CPLDs and FPGAs

Li Shang, Niraj K. Jha, 2001, Proceedings 2001 IEEE International Conference on Computer Design: VLSI in Computers and Processors. ICCD 2001.

A High-level Interconnect Power Model for Design Space Exploration

Niraj K. Jha, Lin Zhong, Pallav Gupta, 2003, ICCAD.

Energy-Efficient Long-term Continuous Personal Health Monitoring

Susmita Sur-Kolay, Niraj K. Jha, Anand Raghunathan, 2015, IEEE Transactions on Multi-Scale Computing Systems.

High-level synthesis of power-optimized and area-optimized circuits from hierarchical data-flow intensive behaviors

Niraj K. Jha, Ganesh Lakshminarayana, 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Power-conscious joint scheduling of periodic task graphs and aperiodic tasks in distributed real-time embedded systems

Niraj K. Jha, Jiong Luo, N. Jha, 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

In-Network Coherence Filtering: Snoopy coherence without broadcasts

Niraj K. Jha, Li-Shiuan Peh, Niket Agarwal, 2009, 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

ROBESim: A retrofit-oriented building energy simulator based on EnergyPlus

Niraj K. Jha, Anand Raghunathan, Jun Wei Chuah, 2013 .

An energy-aware framework for dynamic software management in mobile computing systems

Niraj K. Jha, Lin Zhong, Yunsi Fei, 2008, TECS.

Statistical Optimization of FinFET Processor Architectures under PVT Variations Using Dual Device-Type Assignment

Niraj K. Jha, Ye Yu, N. Jha, 2017, ACM J. Emerg. Technol. Comput. Syst..

Thermal Modeling, Characterization and Management of On-Chip Networks

Li Shang, Niraj K. Jha, Amit Kumar, 2004, 37th International Symposium on Microarchitecture (MICRO-37'04).

Signal Processing With Direct Computations on Compressively Sensed Data

Naveen Verma, Niraj K. Jha, Mohammed Shoaib, 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Fault detection in CVS parity trees: application in SSC CVS parity and two-rail checkers

Niraj K. Jha, 1989, [1989] The Nineteenth International Symposium on Fault-Tolerant Computing. Digest of Papers.

COFTA: hardware-software co-synthesis of heterogeneous distributed embedded system architectures for low overhead fault tolerance

Niraj K. Jha, Bharat P. Dave, N. Jha, 1997, Proceedings of IEEE 27th International Symposium on Fault Tolerant Computing.

Low Power Distributed Embedded Systems: Dynamic Voltage Scaling and Synthesis

Niraj K. Jha, Jiong Luo, N. Jha, 2002, HiPC.

Vibration-based secure side channel for medical devices

Niraj K. Jha, Anand Raghunathan, Vijay Raghunathan, 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).

Fast Enhancement of Validation Test Sets to Improve Stuck-at Fault Coverage for RTL circuits

Niraj K. Jha, Loganathan Lingappan, Vijay Gangaram, 2007, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07).

A Scalable Application-Specific Processor Synthesis Methodology

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2003, ICCAD 2003.

High-level energy macromodeling of embedded software

Niraj K. Jha, Ganesh Lakshminarayana, Tat Kee Tan, 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

A compressed-domain processor for seizure detection to simultaneously reduce computation and communication energy

Naveen Verma, Niraj K. Jha, Mohammed Shoaib, 2012, Proceedings of the IEEE 2012 Custom Integrated Circuits Conference.

Testing of zipper CMOS logic circuits

Niraj K. Jha, Q. Tong, 1990 .

Accurate Leakage Estimation for FinFET Standard Cells Using the Response Surface Methodology

Niraj K. Jha, Prateek Mishra, Sourindra Chaudhuri, 2012, 2012 25th International Conference on VLSI Design.

ChamNet: Towards Efficient Network Design Through Platform-Aware Model Adaptation

Niraj K. Jha, Yiming Wu, Peter Vajda, 2018, 2019 IEEE/CVF Conference on Computer Vision and Pattern Recognition (CVPR).

Power estimation for cycle-accurate functional descriptions of hardware

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..

Synthesis of majority and minority networks and its applications to QCA, TPL and SET based nanotechnologies

Rui Zhang, Niraj K. Jha, Pallav Gupta, 2005, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design.

Robust testing of CMOS logic circuits

Niraj K. Jha, 1989 .

A fast and low cost testing technique for core-based system-on-chip

Sujit Dey, Niraj K. Jha, Indradeep Ghosh, 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

A fast and low-cost testing technique for core-based system-chips

Sujit Dey, Niraj K. Jha, Indradeep Ghosh, 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Testing of zipper CMOS logic circuits

Niraj K. Jha, Q. Tong, 1990, IEEE International Symposium on Circuits and Systems.

Design of totally self-checking checkers for Bose-Lin, Bose and Blaum codes

Niraj K. Jha, 1989, Proceedings of the 32nd Midwest Symposium on Circuits and Systems,.

Hijacking an insulin pump: Security attacks and defenses for a diabetes therapy system

Niraj K. Jha, Anand Raghunathan, Chunxiao Li, 2011, 2011 IEEE 13th International Conference on e-Health Networking, Applications and Services.

FinCANON: A PVT-Aware Integrated Delay and Power Modeling Framework for FinFET-Based Caches and On-Chip Networks

Niraj K. Jha, Chun-Yi Lee, 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A Synthesis Methodology for Hybrid Custom Instruction and Coprocessor Generation for Extensible Processors

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Ultra-low-leakage chip multiprocessor design with hybrid FinFET logic styles

Niraj K. Jha, Xianmin Chen, 2014, JETC.

Thermal Characterization of Test Techniques for FinFET and 3D Integrated Circuits

Niraj K. Jha, Aoxiang Tang, 2013, JETC.

A BIST scheme for RTL controller-data paths based on symbolic testability analysis

Niraj K. Jha, Sudipta Bhawmik, Indradeep Ghosh, 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

Satisfiability-based test generation for nonseparable RTL controller-datapath circuits

Srivaths Ravi, Niraj K. Jha, Loganathan Lingappan, 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Using a Device State Library to Boost the Performance of TCAD Mixed-Mode Simulation

Niraj K. Jha, Xiaoliang Dai, 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

SLOPES: Hardware–Software Cosynthesis of Low-Power Real-Time Distributed Embedded Systems With Dynamically Reconfigurable FPGAs

Li Shang, Niraj K. Jha, Robert P. Dick, 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A framework for testing core-based systems-on-a-chip

Srivaths Ravi, Niraj K. Jha, Ganesh Lakshminarayana, 1999, 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051).

Energy-efficient and Secure Sensor Data Transmission Using Encompression

Meng Zhang, Niraj K. Jha, Anand Raghunathan, 2013, 2013 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems.

Behavioral synthesis for easy testability in data path scheduling

Niraj K. Jha, Tien-Chien Lee, Wayne H. Wolf, 1992, ICCAD.

Smart healthcare

Niraj K. Jha, N. Jha, 2023, 2018 IEEE International Conference on Consumer Electronics (ICCE).

Keep the Stress Away with SoDA: Stress Detection and Alleviation System

Niraj K. Jha, Ayten Ozge Akmandor, N. Jha, 2017, IEEE Transactions on Multi-Scale Computing Systems.

Energy and execution time analysis of a software-based trusted platform module

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2007 .

Efficient fingerprint-based user authentication for embedded systems

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2005, Proceedings. 42nd Design Automation Conference, 2005..

SHARKS: Smart Hacking Approaches for RisK Scanning in Internet-of-Things and Cyber-Physical Systems based on Machine Learning pdf

Niraj K. Jha, Najwa Aaraj, Tanujay Saha, 2021, ArXiv.

Low-power 3D nano/CMOS hybrid dynamically reconfigurable architecture

Wei Zhang, Li Shang, Niraj K. Jha, 2010, JETC.

A scalable application-specific processor synthesis methodology

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2003, ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486).

A personal-area network of low-power wireless interfacing devices for handhelds: system and hardware design

Niraj K. Jha, Lin Zhong, Mike Sinclair, 2005, Mobile HCI.

Input space adaptive embedded software synthesis

Niraj K. Jha, Ganesh Lakshminarayana, Anand Raghunathan, 2002, Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design.

Strong fault-secure and strongly self-checking domino-CMOS implementations of totally self-checking circuits

Niraj K. Jha, 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

RMDDS

Niraj K. Jha, Chia-Chun Lin, N. Jha, 2014, ACM J. Emerg. Technol. Comput. Syst..

Task graph transformation to aid system synthesis

Niraj K. Jha, Keith S. Vallerio, 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

Active Learning Driven Data Acquisition for Sensor Networks

Anish Muttreja, Srivaths Ravi, Niraj K. Jha, 2006, 11th IEEE Symposium on Computers and Communications (ISCC'06).

Exploring Software Partitions for Fast Security

Niraj K. Jha, Anand Raghunathan, Srivaths Ravi, 2007 .

Input space adaptive design: a high-level methodology for energy and performance optimization

Niraj K. Jha, Ganesh Lakshminarayana, Anand Raghunathan, 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

Algorithm-Driven Architectural Design Space Exploration of Domain-Specific Medical-Sensor Processors

Naveen Verma, Niraj K. Jha, Mohammed Shoaib, 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Switching and Finite Automata Theory: Logic design

Niraj K. Jha, Zvi Kohavi, 2009 .

Systematic Poisoning Attacks on and Defenses for Machine Learning in Healthcare

Susmita Sur-Kolay, Niraj K. Jha, Mehran Mozaffari Kermani, 2015, IEEE Journal of Biomedical and Health Informatics.

Design techniques for energy-efficient embedded and mobile computing systems

Niraj K. Jha, Keith S. Vallerio, 2004 .

Design and Synthesis of Self-Checkmg VLSI Circuits

Niraj K. Jha, Sying-Jyan Wang, 1993 .

An evaluation of energy-saving technologies for residential purposes

Niraj K. Jha, Anand Raghunathan, Jun Wei Chuah, 2010, IEEE PES General Meeting.

A low-energy computation platform for data-driven biomedical monitoring algorithms

Naveen Verma, Niraj K. Jha, Mohammed Shoaib, 2011, 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC).

Hardware-Guided Symbiotic Training for Compact, Accurate, yet Execution-Efficient LSTM pdf

Niraj K. Jha, Guoyang Chen, Weifeng Zhang, 2019, ArXiv.

Heterogeneous and multi-level compression techniques for test volume reduction in systems-on-chip

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2005, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design.

Task graph extraction for embedded system synthesis

Niraj K. Jha, Keith S. Vallerio, 2003, 16th International Conference on VLSI Design, 2003. Proceedings..

Synthesis of Quantum Circuits for Dedicated Physical Machine Descriptions

Robert Wille, Niraj K. Jha, Amlan Chakrabarti, 2015, RC.

Architectural support for safe software execution on embedded processors

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2006, Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06).

System-Level Dynamic Thermal Management for High-Performance Microprocessors

Li Shang, Niraj K. Jha, Amit Kumar, 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

SECRET: Semantically Enhanced Classification of Real-World Tasks pdf

Niraj K. Jha, Bongjun Ko, Ayten Ozge Akmandor, 2019, IEEE Transactions on Computers.

Ultra-High Density Monolithic 3-D FinFET SRAM With Enhanced Read Stability

Niraj K. Jha, Debajit Bhattacharya, N. Jha, 2016, IEEE Transactions on Circuits and Systems I: Regular Papers.

High-level synthesis using computation-unit integrated memories

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2004, ICCAD 2004.

A universal test set for CMOS circuits

Niraj K. Jha, Gopal Gupta, 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Detection of multiple input bridging and stuck-on faults in CMOS logic circuits using current monitoring

Niraj K. Jha, Qiao Tong, 1990 .

Software-Defined Design Space Exploration for an Efficient DNN Accelerator Architecture

Niraj K. Jha, Ye Yu, Weifeng Zhang, 2019, IEEE Transactions on Computers.

Design space exploration and data memory architecture design for a hybrid nano/CMOS dynamically reconfigurable architecture

Wei Zhang, Li Shang, Niraj K. Jha, 2009, JETC.

Impact of configurability and extensibility on IPSec protocol execution on embedded processors

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2006, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06).

Niraj K. Jha, Lin Zhong, Jiong Luo, 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Wavesched: A Novel Scheduling Technique For Control-flow Behavioral Descriptions

Niraj K. Jha, Ganesh Lakshminarayana, Kamd S. Khouri, 1997 .

A design for testability technique for RTL circuits using control/data flow extraction

Niraj K. Jha, Anand Raghunathan, Indradeep Ghosh, 1996, Proceedings of International Conference on Computer Aided Design.

Virtualization-assisted Framework for Prevention of Software Vulnerability Based Security Attacks

Niraj K. Jha, Anand Raghunathan, Najwa Aaraj, 2007 .

A conditional resource sharing method for behavioral synthesis of highly testable data paths

Niraj K. Jha, Tien-Chien Lee, Wayne H. Wolf, 1993, Proceedings of IEEE International Test Conference - (ITC).

Exploring Software Partitions for Fast Security Processing on a Multiprocessor Mobile SoC

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

DESIGN OF TOTALLY SELF-CHECKING EMBEDDED CHECKERS.

Niraj K. Jha, Jacob A. Abraham, 1984 .

Compressed Signal Processing on Nyquist-Sampled Signals

Naveen Verma, Niraj K. Jha, Jie Lu, 2016, IEEE Transactions on Computers.

SCALP: an iterative-improvement-based low-power data path synthesis system

Niraj K. Jha, Anand Raghunathan, N. Jha, 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

High-level energy analysis and optimization of operating system-driven embedded software

Niraj K. Jha, T. K. Tan, 2004 .

TAO-BIST: a framework for testability analysis and optimization of RTL circuits for BIST

Srivaths Ravi, Niraj K. Jha, Ganesh Lakshminarayana, 1999, Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146).

Graphical user interface energy characterization for handheld computers

Niraj K. Jha, Lin Zhong, 2003, CASES '03.

Detecting and Alleviating Stress with SoDA

Niraj K. Jha, Ayten Ozge Akmandor, 2018, Computer.

Optimal Design of Checks for Error Detection and Location in Fault-Tolerant Multiprocessor Systems

Niraj K. Jha, Ramesh K. Sitaraman, 1993, IEEE Trans. Computers.

Interconnect-aware high-level synthesis for low power

Niraj K. Jha, Lin Zhong, 2002, IEEE/ACM International Conference on Computer Aided Design, 2002. ICCAD 2002..

Secure reconfiguration of software-defined radio

Niraj K. Jha, Anand Raghunathan, Chunxiao Li, 2012, TECS.

Towards a responsive, yet power-efficient, operating system: a holistic approach

Niraj K. Jha, Lin Zhong, Le Yan, 2005, 13th IEEE International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems.

Energy and Execution Time Analysis of a Software-based Trusted Platform Module

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

Controller re-specification to minimize switching activity in controller/data path circuits

Sujit Dey, Niraj K. Jha, Anand Raghunathan, 1996, ISLPED.

Behavioral synthesis for easy testability in data path scheduling

Niraj K. Jha, Wayne Wolf, Tien-Chien Lee, 1992, 1992 IEEE/ACM International Conference on Computer-Aided Design.

MOGAC: a multiobjective genetic algorithm for the co-synthesis of hardware-software embedded systems

Niraj K. Jha, Robert P. Dick, 1997, ICCAD 1997.

Optimal Design of Checks for Error Detection and Location in Fault Tolerant Multiprocessors Systems

Niraj K. Jha, Ramesh K. Sitaraman, 1991, Fault-Tolerant Computing Systems.

Simultaneously ensuring smartness, security, and energy efficiency in Internet-of-Things sensors

Niraj K. Jha, Hongxu Yin, Ayten Ozge Akmandor, 2018, 2018 IEEE Custom Integrated Circuits Conference (CICC).

Static and dynamic variable voltage scheduling algorithms for real-time heterogeneous distributed embedded systems

Niraj K. Jha, Jiong Luo, 2002, Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design.

Automated Energy/Performance Macromodeling of Embedded Software

Anish Muttreja, Niraj K. Jha, Anand Raghunathan, 2007, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Ultra-low-leakage, Robust FinFET SRAM Design Using Multiparameter Asymmetric FinFETs

Niraj K. Jha, Abdullah Guler, 2016, ACM J. Emerg. Technol. Comput. Syst..

Trustworthiness of Medical Devices and Body Area Networks

Meng Zhang, Niraj K. Jha, Anand Raghunathan, 2014, Proceedings of the IEEE.

Accurate Leakage/Delay Estimation for FinFET Standard Cells under PVT Variations using the Response Surface Methodology

Niraj K. Jha, Prateek Mishra, Sourindra Chaudhuri, 2014, JETC.

High-level synthesis using computation-unit integrated memories

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..

Hierarchical test generation and design for testability methods for ASPPs and ASIPs

Niraj K. Jha, Anand Raghunathan, Indradeep Ghosh, 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Low-power FinFET circuit synthesis using surface orientation optimization

Niraj K. Jha, Prateek Mishra, N. Jha, 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

CMOS logic design with independent-gate FinFETs

Anish Muttreja, Niraj K. Jha, Niket Agarwal, 2007, 2007 25th International Conference on Computer Design.

A hybrid nano/CMOS dynamically reconfigurable system—Part I: Architecture

Wei Zhang, Li Shang, Niraj K. Jha, 2009, JETC.

Design of Testable CMOS Logic Circuits Under Arbitrary Delays

Niraj K. Jha, Jacob A. Abraham, 1985, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Switching and Finite Automata Theory

Niraj K. Jha, Zvi Kohavi, N. Jha, 2010 .

Threshold network synthesis and optimization and its application to nanotechnologies

Rui Zhang, Niraj K. Jha, Lin Zhong, 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

: a novel scheduling technique for control-flow intensive behavioral descriptions

Niraj K. Jha, Ganesh Lakshminarayana, K. S. Khouri, 1997, ICCAD 1997.

A totally self-checking checker for a parallel unordered coding scheme

Niraj K. Jha, Steven W. Burns, 1992, Digest of Papers. 1992 IEEE VLSI Test Symposium.

Hybrid Simulation for Energy Estimation of Embedded Software

Anish Muttreja, Srivaths Ravi, Niraj K. Jha, 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

In-Network Snoop Ordering (INSO): Snoopy coherence on unordered interconnects

Niraj K. Jha, Li-Shiuan Peh, Niket Agarwal, 2009, 2009 IEEE 15th International Symposium on High Performance Computer Architecture.

Test generation for non-separable RTL controller-datapath circuits using a satisfiability based approach

Srivaths Ravi, Niraj K. Jha, Loganathan Lingappan, 2003, Proceedings 21st International Conference on Computer Design.

Fault modeling for FinFET circuits

Niraj K. Jha, Muzaffer O. Simsir, Ajay N. Bhoj, 2010, 2010 IEEE/ACM International Symposium on Nanoscale Architectures.

An iterative improvement algorithm for low power data path synthesis

Niraj K. Jha, Anand Raghunathan, N. Jha, 1995, ICCAD.

FACT: a framework for the application of throughput and power optimizing transformations to control-flow intensive behavioral descriptions

Niraj K. Jha, Ganesh Lakshminarayana, N. Jha, 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

A 3-D CPU-FPGA-DRAM Hybrid Architecture for Low-Power Computation

Niraj K. Jha, Xianmin Chen, N. Jha, 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Analysis and Randomized Design of Algorithm-Based Fault Tolerant Multiprocessor Systems Under an Extended Model

Niraj K. Jha, Shalini Yajnik, 1997, IEEE Trans. Parallel Distributed Syst..

Parasitics-Aware Design of Symmetric and Asymmetric Gate-Workfunction FinFET SRAMs

Niraj K. Jha, Ajay N. Bhoj, 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Easily testable nonrestoring and restoring gate-level cellular array dividers

Niraj K. Jha, Abha Ahuja, N. Jha, 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Evaluating Conditional Statements in Embedded System Software: Systematic Methodologies for Reducing Energy Consumption

Niraj K. Jha, Keith S. Vallerio, N. Jha, 2004, ESA/VLSI.

Unsatisfiability based efficient design for testability solution for register-transfer level circuits

Niraj K. Jha, Loganathan Lingappan, 2005, 23rd IEEE VLSI Test Symposium (VTS'05).

Energy-efficient graphical user interface design

Niraj K. Jha, Lin Zhong, Keith S. Vallerio, 2004, IEEE Transactions on Mobile Computing.

Memory binding for performance optimization of control-flow intensive behaviors

Niraj K. Jha, Ganesh Lakshminarayana, Kamal S. Khouri, 1999, 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051).

Secure embedded processing through hardware-assisted run-time monitoring

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2005, Design, Automation and Test in Europe.

Testing of Digital Systems

Niraj K. Jha, Sandeep Gupta, 2003 .

Behavioral synthesis of fault secure controller/datapaths using aliasing probability analysis

Niraj K. Jha, Ganesh Lakshminarayana, Anand Raghunathan, 1996, Proceedings of Annual Symposium on Fault Tolerant Computing.

MACHETE: synthesis of sequential machines for easy testability

Bapiraju Vinnakota, Niraj K. Jha, 1991, Proceedings of the European Conference on Design Automation..

Embedded operating system energy analysis and macro-modeling

Niraj K. Jha, Anand Raghunathan, Tat Kee Tan, 2002, Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors.

A low overhead design for testability and test generation technique for core-based systems-on-a-chip

Sujit Dey, Niraj K. Jha, Indradeep Ghosh, 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Energy macromodeling of embedded operating systems

Niraj K. Jha, Anand Raghunathan, Tat Kee Tan, 2005, TECS.

A design for testability technique for RTL circuits using control/data flow extraction

Niraj K. Jha, Indradeep Ghosh, Anand Raghunathan, 1996, ICCAD 1996.

STEERAGE: Synthesis of Neural Networks Using Architecture Search and Grow-and-Prune Methods pdf

Niraj K. Jha, Xiaoliang Dai, Shayan Hassantabar, 2019, ArXiv.

Interconnect-aware low-power high-level synthesis

Niraj K. Jha, Lin Zhong, N. Jha, 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Algorithm-based fault tolerance for floating-point operations in massively parallel systems

Niraj K. Jha, Jennifer Rexford, 1992, [Proceedings] 1992 IEEE International Symposium on Circuits and Systems.

Design of Algorithm-Based Fault-Tolerant Multiprocessor Systems for Concurrent Error Detection and Fault Diagnosis

Bapiraju Vinnakota, Niraj K. Jha, 1994, IEEE Trans. Parallel Distributed Syst..

Robustly testable static CMOS parity trees derived from binary decision diagrams

Niraj K. Jha, Q. Tong, 1991 .

FinFET Logic Circuit Optimization with Different FinFET Styles: Lower Power Possible at Higher Supply Voltage

Niraj K. Jha, Sourindra Chaudhuri, 2014, 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems.

Satisfiability-Based Automatic Test Program Generation and Design for Testability for Microprocessors

Niraj K. Jha, Loganathan Lingappan, 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Test Generation for Static CMOS Circuits

Niraj K. Jha, Sandip Kundu, 1990 .

Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability

Niraj K. Jha, Steven M. Nowick, Fu-Chiung Cheng, 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Power-Aware Architectural Synthesis

Niraj K. Jha, Robert P. Dick, Li Shang, 2007 .

Design of C-testable DCVS binary array dividers

Niraj K. Jha, Q. Tong, 1991 .

Controller-based power management for control-flow intensive designs

Sujit Dey, Niraj K. Jha, Anand Raghunathan, 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

COWLS: hardware-software cosynthesis of wireless low-power distributed embedded client-server systems

Niraj K. Jha, Robert P. Dick, N. Jha, 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Power management techniques for control-flow intensive designs

Sujit Dey, Niraj K. Jha, Anand Raghunathan, 1997, DAC.

FinFET-based dynamic power management of on-chip interconnection networks through adaptive back-gate biasing

Niraj K. Jha, Chun-Yi Lee, 2009, 2009 IEEE International Conference on Computer Design.

Towards trustworthy medical devices and body area networks

Meng Zhang, Niraj K. Jha, Anand Raghunathan, 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).

Profiling driven computation reuse: an embedded software synthesis technique for energy and performance optimization

Niraj K. Jha, Anand Raghunathan, Weidong Wang, 2004, 17th International Conference on VLSI Design. Proceedings..

SRAM-Based NATURE: A Dynamically Reconfigurable FPGA Based on 10T Low-Power SRAMs

Wei Zhang, Niraj K. Jha, Ting-Jung Lin, 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A Fine-Grain Dynamically Reconfigurable Architecture Aimed at Reducing the FPGA-ASIC Gaps

Wei Zhang, Niraj K. Jha, Ting-Jung Lin, 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

RTL-Aware Cycle-Accurate Functional Power Estimation

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

An Economics-based Power-aware Protocol for Computation Distribution in Mobile Ad-Hoc Networks

Li Shang, Niraj K. Jha, Robert P. Dick, 2002, IASTED PDCS.

Systematic t-error correcting/all unidirectional error detecting codes with easy encoding/decoding

Niraj K. Jha, Sying-Jyan Wang, 1990 .

Three-Dimensional Monolithic FinFET-Based 8T SRAM Cell Design for Enhanced Read Time and Low Leakage

Niraj K. Jha, Abdullah Guler, N. Jha, 2019, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A technique for identifying RTL and gate-level correspondences

Srivaths Ravi, Niraj K. Jha, Vamsi Boppana, 2000, Proceedings 2000 International Conference on Computer Design.

Fully Dynamic Inference With Deep Neural Networks pdf

Niraj K. Jha, Xiaoliang Dai, Hongxu Yin, 2020, IEEE Transactions on Emerging Topics in Computing.

Design and synthesis of self-checking VLSI circuits and systems

Niraj K. Jha, Sying-Jyan Wang, 1991, [1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors.

A dependence graph-based approach to the design of algorithm-based fault tolerant systems

Bapiraju Vinnakota, Niraj K. Jha, 1990, [1990] Digest of Papers. Fault-Tolerant Computing: 20th International Symposium.

TCAD-Assisted Capacitance Extraction of FinFET SRAM and Logic Arrays

Niraj K. Jha, Debajit Bhattacharya, 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

High-level macro-modeling and estimation techniques for switching activity and power consumption

Sujit Dey, Niraj K. Jha, Anand Raghunathan, 2003, IEEE Trans. Very Large Scale Integr. Syst..

Design of Logic Gates and Flip-Flops in High-Performance FinFET Technology

Niraj K. Jha, Ajay N. Bhoj, N. Jha, 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Sub-threshold Computational Circuits for High-order Data-driven Analysis of Physiological Signals

Naveen Verma, Niraj K. Jha, Shuayb Zarar, 2011 .

Synthesis of Algorithm-Based Fault-Tolerant Systems from Dependence Graphs

Bapiraju Vinnakota, Niraj K. Jha, 1993, IEEE Trans. Parallel Distributed Syst..

Removal of memory access bottlenecks for scheduling control-flow intensive behavioral descriptions

Srivaths Ravi, Niraj K. Jha, Ganesh Lakshminarayana, 1998, 1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287).

High-level synthesis of distributed logic-memory architectures

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2002, ICCAD 2002.

Hybrid Monolithic 3-D IC Floorplanner

Niraj K. Jha, Abdullah Guler, N. Jha, 2018, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Synthesis of Heterogeneous Distributed Architectures for Memory-Intensive Applications

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2003, ICCAD 2003.

Wavesched: a novel scheduling technique for control-flow intensive behavioral descriptions

Niraj K. Jha, Ganesh Lakshminarayana, Kamal S. Khouri, 1997, 1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

A 4.6Tbits/s 3.6GHz single-cycle NoC router with a novel switch allocator in 65nm CMOS

Niraj K. Jha, Amit Kumar, Li-Shiuan Peh, 2007, ICCD.

COSYN: Hardware-software co-synthesis of heterogeneous distributed embedded systems

Niraj K. Jha, Ganesh Lakshminarayana, Bharat P. Dave, 1999, IEEE Trans. Very Large Scale Integr. Syst..

A 0.6–107 µW Energy-Scalable Processor for Directly Analyzing Compressively-Sensed EEG

Naveen Verma, Niraj K. Jha, Kyong-Ho Lee, 2014, IEEE Transactions on Circuits and Systems I: Regular Papers.

Easily testable gate-level and DCVS multipliers

Niraj K. Jha, Andres R. Takach, 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

A Comprehensive Study of Security of Internet-of-Things

Niraj K. Jha, Arsalan Mosenia, N. Jha, 2017, IEEE Transactions on Emerging Topics in Computing.

Dynamic voltage scaling with links for power optimization of interconnection networks

Li Shang, Niraj K. Jha, Li-Shiuan Peh, 2003, The Ninth International Symposium on High-Performance Computer Architecture, 2003. HPCA-9 2003. Proceedings..

FinFETs: From Devices to Architectures

Niraj K. Jha, Debajit Bhattacharya, 2014 .

Aiding Side-Channel Attacks on Cryptographic Software With Satisfiability-Based Analysis

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Analytical Modeling of the SMART NoC

Niraj K. Jha, Debajit Bhattacharya, 2017, IEEE Transactions on Multi-Scale Computing Systems.

High-level synthesis of distributed logic-memory architectures

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2002, IEEE/ACM International Conference on Computer Aided Design, 2002. ICCAD 2002..

A simulation framework for energy-consumption analysis of OS-driven embedded applications

Niraj K. Jha, Anand Raghunathan, Tat Kee Tan, 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Power management in high-level synthesis

Sujit Dey, Niraj K. Jha, Ganesh Lakshminarayana, 1999, IEEE Trans. Very Large Scale Integr. Syst..

Application-specific heterogeneous multiprocessor synthesis using extensible processors

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A Hybrid Nano/CMOS Dynamically Reconfigurable System

Li Shang, Niraj K. Jha, Wei Zhang, 2011 .

Threshold Voltage Control through Multiple Supply Voltages for Power-Efficient FinFET Interconnects

Anish Muttreja, Niraj K. Jha, Prateek Mishra, 2008, 21st International Conference on VLSI Design (VLSID 2008).

Synthesis of system-on-a-chip for testability

Srivaths Ravi, Niraj K. Jha, N. Jha, 2001, VLSI Design 2001. Fourteenth International Conference on VLSI Design.

Making buildings energy-efficient through retrofits: A survey of available technologies

Niraj K. Jha, Jun Wei Chuah, Sreya Basuroy, 2013, 2013 IEEE Power & Energy Society General Meeting.

Design of Quantum Circuits for Random Walk Algorithms

Niraj K. Jha, Amlan Chakrabarti, Chia-Chun Lin, 2012, 2012 IEEE Computer Society Annual Symposium on VLSI.

Software architectural transformations: a new approach to low energy embedded software

Niraj K. Jha, Anand Raghunathan, Tat Kee Tan, 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

State encoding of finite-state machines targeting threshold and majority logic based implementations with application to nanotechnologies

Rui Zhang, Niraj K. Jha, N. Jha, 2006, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06).

Express virtual channels: towards the ideal interconnection fabric

Niraj K. Jha, Amit Kumar, Li-Shiuan Peh, 2007, ISCA '07.

Energy-Efficient Monolithic Three-Dimensional On-Chip Memory Architectures

Niraj K. Jha, Ye Yu, N. Jha, 2018, IEEE Transactions on Nanotechnology.

Guest Editorial

Niraj K. Jha, 1998, J. Electron. Test..

Energy-optimizing source code transformations for OS-driven embedded software

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2004, 17th International Conference on VLSI Design. Proceedings..

Transforming control-flow intensive designs to facilitate power management

Sujit Dey, Niraj K. Jha, Ganesh Lakshminarayana, 1998, ICCAD.

Improving the performance of automatic sequential test generation by targeting hard-to-test faults

Niraj K. Jha, Loganathan Lingappan, 2006, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06).

Synthesis of sequential circuits for easy testability through performance-oriented parallel partial scan

Niraj K. Jha, Sandeep Bhatia, 1993, Proceedings of 1993 IEEE International Conference on Computer Design ICCD'93.

Energy estimation for extensible processors

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

Incorporating speculative execution into scheduling of control-flow intensive behavioral descriptions

Niraj K. Jha, Ganesh Lakshminarayana, Anand Raghunathan, 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

Test synthesis of systems-on-a-chip

Srivaths Ravi, Niraj K. Jha, N. Jha, 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Testing and Reliable Design of CMOS Circuits

Niraj K. Jha, Sandip Kundu, N. Jha, 1989 .

An algorithm for nano-pipelining of circuits and architectures for a nanotechnology

Niraj K. Jha, Pallav Gupta, N. Jha, 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

COHRA: hardware-software co-synthesis of hierarchical distributed embedded system architectures

Niraj K. Jha, Bharat P. Dave, 1998, Proceedings Eleventh International Conference on VLSI Design.

Safety and Reliability Driven Task Allocation in Distributed Systems

Niraj K. Jha, Santhanam Srinivasan, N. Jha, 1999, IEEE Trans. Parallel Distributed Syst..

HybDTM: a coordinated hardware-software approach for dynamic thermal management

Li Shang, Niraj K. Jha, Amit Kumar, 2006, 2006 43rd ACM/IEEE Design Automation Conference.

A heterogeneous microprocessor for energy-scalable sensor inference using genetic programming

Hongyang Jia, Niraj K. Jha, Jie Lu, 2017, 2017 Symposium on VLSI Circuits.

Synthesis of Heterogeneous Distributed Architectures for Memory-Intensive Applications

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2003, ICCAD.

Analysis of power dissipation in embedded systems using real-time operating systems

Niraj K. Jha, Ganesh Lakshminarayana, Anand Raghunathan, 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Secure Embedded Processing through Hardware-assisted

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2005 .

Token flow control

Niraj K. Jha, Amit Kumar, Li-Shiuan Peh, 2008, 2008 41st IEEE/ACM International Symposium on Microarchitecture.

Detection of multiple input bridging and stuck-on faults in CMOS logic circuits using current monitoring

Niraj K. Jha, Carol Q. Tong, 1990, Proceedings of the European Design Automation Conference, 1990., EDAC..

Eliminating memory bottlenecks for a JPEG encoder through distributed logic-memory architecture and computation-unit integrated memory

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2005, Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005..

A study of the energy consumption characteristics of cryptographic algorithms and security protocols

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2006, IEEE Transactions on Mobile Computing.

CACTI-FinFET: An integrated delay and power modeling framework for FinFET-based caches under process variations

Niraj K. Jha, Chun-Yi Lee, 2011, 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC).

Evaluation of multiple supply and threshold voltages for low-power FinFET circuit synthesis

Anish Muttreja, Niraj K. Jha, Prateek Mishra, 2008, 2008 IEEE International Symposium on Nanoscale Architectures.

Detecting Multiple Faults in CMOS Circuits

Niraj K. Jha, N. Jha, 1986, ITC.

TOTALLY SELF-CHECKING CMOS CIRCUITS USING A HYBRID REALIZATION.

Niraj K. Jha, Jacob A. Abraham, N. Jha, 1985 .

Low-power system scheduling, synthesis and displays

Niraj K. Jha, N. Jha, 2005 .

Power-Efficient Scheduling for Heterogeneous Distributed Real-Time Embedded Systems

Niraj K. Jha, Jiong Luo, N. Jha, 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Testing of core-based systems-on-a-chip

Srivaths Ravi, Niraj K. Jha, Ganesh Lakshminarayana, 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

INVITED: Efficient Synthesis of Compact Deep Neural Networks

Niraj K. Jha, Hongxu Yin, Wenhan Xia, 2020, 2020 57th ACM/IEEE Design Automation Conference (DAC).

COFTA : Hardware-Software Co-Synthesis of Heterogeneous Distributed Embedded Systems for Low Overhead Fault Tolerance

Niraj K. Jha, Bharat P. Dave, N. Jha, 1999 .

CORDS: hardware-software co-synthesis of reconfigurable real-time distributed embedded systems

Niraj K. Jha, Robert P. Dick, 1998, ICCAD.

Grow and Prune Compact, Fast, and Accurate LSTMs

Niraj K. Jha, Xiaoliang Dai, Hongxu Yin, 2018, IEEE Transactions on Computers.

Improving Convergence and Simulation Time of Quantum Hydrodynamic Simulation: Application to Extraction of Best 10-nm FinFET Parameter Values

Niraj K. Jha, Xiaoliang Dai, 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Architectural Support for Run-Time Validation of Program Data Properties

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A system-level perspective for efficient NoC design

Niraj K. Jha, Amit Kumar, Li-Shiuan Peh, 2008, 2008 IEEE International Symposium on Parallel and Distributed Processing.

Efficient Design for Testability Solution Based on Unsatisfiability for Register-Transfer Level Circuits

Niraj K. Jha, Loganathan Lingappan, N. Jha, 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

An automatic test pattern generation framework for combinational threshold logic networks

Rui Zhang, Niraj K. Jha, Pallav Gupta, 2004, IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings..

Delay/Power Modeling and Optimization of FinFET Circuit Modules under PVT Variations

Niraj K. Jha, Aoxiang Tang, Xun Gao, 2016, ACM J. Emerg. Technol. Comput. Syst..

A Trusted Virtual Machine in an Untrusted Management Environment

Niraj K. Jha, Anand Raghunathan, Chunxiao Li, 2012, IEEE Transactions on Services Computing.

TOTALLY SELF-CHECKING MOS CIRCUITS UNDER REALISTIC PHYSICAL FAILURES.

Niraj K. Jha, Jacob A. Abraham, N. Jha, 1984 .

Design and analysis of fault-detecting and fault-locating schedules for computation DAGs

Niraj K. Jha, Shalini Yajnik, 1992, Proceedings Sixth International Parallel Processing Symposium.

A BIST scheme for RTL circuits based on symbolic testabilityanalysis

Niraj K. Jha, Sudipta Bhawmik, Indradeep Ghosh, 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

CovidDeep: SARS-CoV-2/COVID-19 Test Based on Wearable Medical Sensors and Efficient Neural Networks pdf

Niraj K. Jha, Raffaele Bruno, Alessandra Ferrari, 2020, IEEE Transactions on Consumer Electronics.

FinPrin: FinFET Logic Circuit Analysis and Optimization Under PVT Variations

Niraj K. Jha, Yang Yang, 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Power analysis of embedded operating systems

Niraj K. Jha, Ganesh Lakshminarayana, Anand Raghunathan, 2000, Proceedings 37th Design Automation Conference.

Incremental Learning Using a Grow-and-Prune Paradigm With Efficient Neural Networks pdf

Niraj K. Jha, Xiaoliang Dai, Hongxu Yin, 2019, IEEE Transactions on Emerging Topics in Computing.

Incorporating speculative execution into scheduling ofcontrol-flow-intensive designs

Niraj K. Jha, Ganesh Lakshminarayana, Anand Raghunathan, 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Custom-instruction synthesis for extensible-processor platforms

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

TCAD structure synthesis and capacitance extraction of a voltage-controlled oscillator using automated layout-to-device synthesis methodology

Rajiv V. Joshi, Niraj K. Jha, Herschel A. Ainspan, 2014, Proceedings of the IEEE 2014 Custom Integrated Circuits Conference.

Energy-efficient mobile system design: the user's perspective

Niraj K. Jha, Lin Zhong, N. Jha, 2005 .

Smart Health Care: An Edge-Side Computing Perspective

Niraj K. Jha, Ayten Ozge Akmandor, N. Jha, 2018, IEEE Consumer Electronics Magazine.

Design of sufficiently strongly self-checking embedded checkers for systematic and separable codes

Niraj K. Jha, 1989, Proceedings 1989 IEEE International Conference on Computer Design: VLSI in Computers and Processors.

PowerHerd: a distributed scheme for dynamically satisfying peak-power constraints in interconnection networks

Li Shang, Niraj K. Jha, Li-Shiuan Peh, 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Functional partitioning for low power distributed systems of systems-on-a-chip

Niraj K. Jha, Yunsi Fei, 2002, Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design.

An architecture for secure software defined radio

Niraj K. Jha, Anand Raghunathan, Chunxiao Li, 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

Internet-of-Medical-Things

Niraj K. Jha, N. Jha, 2017, ACM Great Lakes Symposium on VLSI.

Self-Checking Circuits

Niraj K. Jha, Sandip Kundu, 1990 .

High-level synthesis of multi-process behavioral descriptions

Sujit Dey, Niraj K. Jha, Anand Raghunathan, 2003, 16th International Conference on VLSI Design, 2003. Proceedings..

Clock selection for performance optimization of control-flow intensive behaviors

Niraj K. Jha, Kamal S. Khouri, N. Jha, 2000, VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design.

A hybrid Nano/CMOS dynamically reconfigurable system—Part II: Design optimization flow

Wei Zhang, Li Shang, Niraj K. Jha, 2009, JETC.

Power estimation for cycle-accurate functional descriptions of hardware

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2004, ICCAD 2004.

McPAT-Monolithic: An Area/Power/Timing Architecture Modeling Framework for 3-D Hybrid Monolithic Multicore Systems

Niraj K. Jha, Abdullah Guler, 2020, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Analyzing the energy consumption of security protocols

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2003, ISLPED '03.

Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability

Niraj K. Jha, Steven M. Nowick, Fu-Chiung Cheng, 1995, Proceedings of the 8th International Conference on VLSI Design.

Diagnosability and diagnosis of algorithm-based fault tolerant systems

Niraj K. Jha, B. Vinnakota, 1989, Proceedings of the 32nd Midwest Symposium on Circuits and Systems,.

Software architecture exploration for high-performance security processing on a multiprocessor mobile SoC

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2006, 2006 43rd ACM/IEEE Design Automation Conference.

Synthesis of sequential circuits for parallel scan

Niraj K. Jha, B. Vinnakota, B. Vinnakota, 1992, [1992] Proceedings The European Conference on Design Automation.

Sujit Dey, Niraj K. Jha, Anand Raghunathan, 1996, Proceedings of International Conference on Computer Aided Design.

PinMe: Tracking a Smartphone User around the World

Niraj K. Jha, Prateek Mittal, Xiaoliang Dai, 2018, IEEE Transactions on Multi-Scale Computing Systems.

Synthesis of custom processors based on extensible platforms

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2002, IEEE/ACM International Conference on Computer Aided Design, 2002. ICCAD 2002..

Synthesis of application-specific heterogeneous multiprocessor architectures using extensible processors

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2005, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design.

Switching and Finite Automata Theory: Frontmatter

Niraj K. Jha, Zvi Kohavi, Zvi Kohavi, 2009 .

YSUY: Your Smartphone Understands You—Using Machine Learning to Address Fundamental Human Needs

Niraj K. Jha, Xiaoliang Dai, Ayten Ozge Akmandor, 2021, IEEE Transactions on Systems, Man, and Cybernetics: Systems.

A design-for-testability technique for register-transfer level circuits using control/data flow extraction

Niraj K. Jha, Anand Raghunathan, Indradeep Ghosh, 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

TEST GENERATION FRAMEWORK FOR COMBINATIONAL QUANTUM CELLULAR AUTOMATA CIRCUITS

Niraj K. Jha, P Gupta, L Lingappan, 2007 .

Design of ultra-low-leakage logic gates and flip-flops in high-performance FinFET technology

Niraj K. Jha, Ajay N. Bhoj, 2011, 2011 12th International Symposium on Quality Electronic Design.

FTQLS: Fault-Tolerant Quantum Logic Synthesis

Niraj K. Jha, Amlan Chakrabarti, Chia-Chun Lin, 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

DESP: a distributed economics-based subcontracting protocol for computation distribution in power-aware mobile ad hoc networks

Li Shang, Niraj K. Jha, Robert P. Dick, 2004, IEEE Transactions on Mobile Computing.

Behavioral synthesis for easy testability in data path allocation

Niraj K. Jha, Tien-Chien Lee, Wayne H. Wolf, 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.

MINIMALIST: An Environment for the Synthesis, Verification and Testability of Burst-Mode Asynchronous Machines

Niraj K. Jha, Bill Lin, Luis A. Plana, 1999 .

Combined Dynamic Voltage Scaling and Adaptive Body Biasing for Heterogeneous Distributed Real-time Embedded Systems

Niraj K. Jha, Jiong Luo, Le Yan, 2003, ICCAD.

PAQCS: Physical Design-Aware Fault-Tolerant Quantum Circuit Synthesis

Susmita Sur-Kolay, Niraj K. Jha, Chia-Chun Lin, 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A new class of symmetric error correcting/unidirectional error detecting codes

Niraj K. Jha, 1988, Proceedings 1988 IEEE International Conference on Computer Design: VLSI.

Automatic Test Generation for Combinational Threshold Logic Networks

Niraj K. Jha, Rui Zhang, Pallav Gupta, 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Enabling advanced inference on sensor nodes through direct use of compressively-sensed signals

Naveen Verma, Niraj K. Jha, Mohammed Shoaib, 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

McPAT-PVT: Delay and Power Modeling Framework for FinFET Processor Architectures Under PVT Variations

Niraj K. Jha, Yang Yang, Aoxiang Tang, 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Fast test generation for circuits with RTL and gate-level views

Srivaths Ravi, Niraj K. Jha, N. Jha, 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

Energy-optimizing source code transformations for operating system-driven embedded software

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2007, TECS.

Simultaneous Dynamic Voltage Scaling of Processors and Communication Links in Real-Time Distributed Embedded Systems

Niraj K. Jha, Li-Shiuan Peh, Jiong Luo, 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

TUTOR: Training Neural Networks Using Decision Rules as Model Priors pdf

Niraj K. Jha, Prerit Terway, Shayan Hassantabar, 2020, ArXiv.

Dreaming to Distill: Data-Free Knowledge Transfer via DeepInversion

Niraj K. Jha, Pavlo Molchanov, Jan Kautz, 2020, 2020 IEEE/CVF Conference on Computer Vision and Pattern Recognition (CVPR).

Design and Analysis of Algorithm-Based Fault Tolerant Multiprocessor Systems

Niraj K. Jha, Shalini Yajnik, 1994 .

Fast high-level power estimation for control-flow intensive designs

Niraj K. Jha, Ganesh Lakshminarayana, Kamal S. Khouri, 1998, Proceedings. 1998 International Symposium on Low Power Electronics and Design (IEEE Cat. No.98TH8379).

Controller re-specification to minimize switching activity in controller/data path circuits

Niraj K. Jha, Anand Raghunathan, Kazutoshi Wakabayashi, 1996, Proceedings of 1996 International Symposium on Low Power Electronics and Design.

Power-efficient Interconnection Networks: Dynamic Voltage Scaling with Links

Li Shang, Niraj K. Jha, Li-Shiuan Peh, 2002, IEEE Computer Architecture Letters.

INVISIOS: A Lightweight, Minimally Intrusive Secure Execution Environment

Niraj K. Jha, Anand Raghunathan, Najwa Aaraj, 2012, TECS.

A hybrid energy-estimation technique for extensible processors

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

TAO-BIST: A framework for testability analysis and optimization forbuilt-in self-test of RTL circuits

Srivaths Ravi, Niraj K. Jha, Ganesh Lakshminarayana, 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Automated Energy/Performance Macromodeling of Embedded Software

Anish Muttreja, Srivaths Ravi, Niraj K. Jha, 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A defense framework against malware and vulnerability exploits

Meng Zhang, Niraj K. Jha, Anand Raghunathan, 2014, International Journal of Information Security.

High-level synthesis of low-power control-flow intensive circuits

Niraj K. Jha, Ganesh Lakshminarayana, Kamal S. Khouri, 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

IMPACT: A high-level synthesis system for low power control-flow intensive circuits

Niraj K. Jha, Ganesh Lakshminarayana, Kamal S. Khouri, 1998, Proceedings Design, Automation and Test in Europe.

Design of robustly testable combinational logic circuits

Sudhakar M. Reddy, Niraj K. Jha, Sandip Kundu, 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Hybrid custom instruction and co-processor synthesis methodology for extensible processors

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2006, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06).

COHRA: hardware-software cosynthesis of hierarchical heterogeneous distributed embedded systems

Niraj K. Jha, Bharat P. Dave, N. Jha, 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Fault Tolerant Parallel Computing in Orthogonal Shared-Memory and Related Architectures

Niraj K. Jha, Isaac D. Scherson, 1992 .

MedMon: A Novel Device for Monitoring Medical Device Security

Niraj K. Jha, Anand Raghunathan, Meng Zhang, 2012 .

Joint dynamic voltage scaling and adaptive body biasing for heterogeneous distributed real-time embedded systems

Niraj K. Jha, Jiong Luo, Le Yan, 2003, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A power management methodology for high-level synthesis

Sujit Dey, Niraj K. Jha, Ganesh Lakshminarayana, 1998, Proceedings Eleventh International Conference on VLSI Design.

Memory binding for performance optimization of control-flow intensive behavioral descriptions

Niraj K. Jha, Ganesh Lakshminarayana, Kamal S. Khouri, 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

NanoV: Nanowire-based VLSI design

Niraj K. Jha, Muzaffer O. Simsir, M. O. Simsir, 2010, 2010 IEEE/ACM International Symposium on Nanoscale Architectures.

An Algorithm for Synthesis of Reversible Logic Circuits

Niraj K. Jha, Pallav Gupta, Abhinav Agrawal, 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Test Generation for Dynamic CMOS Circuits

Niraj K. Jha, Sandip Kundu, 1990 .

Task Allocation for Safety and Reliability in Distributed Systems

Niraj K. Jha, Santhanam Srinivasan, 1995, ICPP.

Switching and Finite Automata Theory: Introduction to synchronous sequential circuits and iterative networks

Niraj K. Jha, Zvi Kohavi, N. Jha, 2009 .

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Radu Marculescu, Majid Sarrafzadeh, Vishwani D. Agrawal, 2018, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Battery-aware static scheduling for distributed real-time embedded systems

Niraj K. Jha, Jiong Luo, 2001, DAC '01.

3D vs. 2D analysis of FinFET logic gates under process variations

Niraj K. Jha, Sourindra Chaudhuri, N. Jha, 2011, 2011 IEEE 29th International Conference on Computer Design (ICCD).

Design for hierarchical testability of RTL circuits obtained by behavioral synthesis

Niraj K. Jha, Anand Raghunathan, Indradeep Ghosh, 1995, Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors.

Algorithm-based fault tolerance for FFT networks

Niraj K. Jha, Sying-Jyan Wang, 1992, [Proceedings] 1992 IEEE International Symposium on Circuits and Systems.

Language Selection for Mobile Systems: Java, C, or Both?

Niraj K. Jha, Keith S. Vallerio, 2004, ESA/VLSI.

A Scalable Synthesis Methodology for Application-Specific Processors

Srivaths Ravi, Niraj K. Jha, Fei Sun, 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Testing of combinational circuits

Niraj K. Jha, Zvi Kohavi, 2009 .

Niraj K. Jha, Anand Raghunathan, Sujit Dey, 1996, ICCAD 1996.

gem5-PVT

Niraj K. Jha, Xianmin Chen, 2015, ACM J. Emerg. Technol. Comput. Syst..

MedMon: Securing Medical Devices Through Wireless Monitoring and Anomaly Detection

Meng Zhang, Niraj K. Jha, Anand Raghunathan, 2013, IEEE Transactions on Biomedical Circuits and Systems.

TECHNIQUES FOR EFFICIENT MOS IMPLEMENTATION OF TOTALLY SELF-CHECKING CHECKERS.

Niraj K. Jha, Jacob A. Abraham, 1985 .

Fault Detection in CVS Parity Trees with Application to Strongly Self-Checking Parity and Two-Rail Checkers

Niraj K. Jha, 1993, IEEE Trans. Computers.

TESTABLE CMOS LOGIC CIRCUITS UNDER DYNAMIC BEHAVIOR.

Niraj K. Jha, Jacob A. Abraham, 1984 .

Low power system scheduling and synthesis

Niraj K. Jha, N. Jha, 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).

FDR 2.0: A Low-Power Dynamically Reconfigurable Architecture and Its FinFET Implementation

Wei Zhang, Niraj K. Jha, Ting-Jung Lin, 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

FACT: a framework for applying throughput and power optimizing transformations to control-flow-intensive behavioral descriptions

Niraj K. Jha, Ganesh Lakshminarayana, N. Jha, 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Design of robustly testable static CMOS parity trees derived from binary decision diagrams

Niraj K. Jha, Carol Q. Tong, 1990, Proceedings., 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors.

Fault-tolerant computer system design

Niraj K. Jha, N. Jha, 1996, IEEE Parallel & Distributed Technology: Systems & Applications.

Hybrid simulation for embedded software energy estimation

Anish Muttreja, Srivaths Ravi, Niraj K. Jha, 2005, Proceedings. 42nd Design Automation Conference, 2005..

Synthesis and optimization of threshold logic networks with application to nanotechnologies

Rui Zhang, Niraj K. Jha, Lin Zhong, 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

Secure Virtual Machine Execution under an Untrusted Management OS

Niraj K. Jha, Anand Raghunathan, Chunxiao Li, 2010, 2010 IEEE 3rd International Conference on Cloud Computing.

Data-driven techniques for hardware and software synthesis for embedded systems

Niraj K. Jha, Weidong Wang, 2004 .

Integration of hierarchical test generation with behavioral synthesis of controller and data path circuits

Niraj K. Jha, Sandeep Bhatia, N. Jha, 1998, IEEE Trans. Very Large Scale Integr. Syst..

Niraj K. Jha, Lin Zhong, Jiong Luo, 2002, Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors.

Glitch analysis and reduction in register transfer level power optimization

Sujit Dey, Niraj K. Jha, Anand Raghunathan, 1996, DAC '96.

High-Level Synthesis for Low Power

Niraj K. Jha, Anand Raghunathan, Sujit Dey, 1998 .

3-D-TCAD-Based Parasitic Capacitance Extraction for Emerging Multigate Devices and Circuits

Rajiv V. Joshi, Niraj K. Jha, Ajay N. Bhoj, 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Clock selection for performance optimization of control-flowintensive behaviors

Niraj K. Jha, Kamal S. Khouri, 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

A Monolithic 3D Hybrid Architecture for Energy-Efficient Computation

Niraj K. Jha, Ye Yu, N. Jha, 2018, IEEE Transactions on Multi-Scale Computing Systems.

High-Level Synthesis Algorithms for Power and Temperature Minimization

Niraj K. Jha, Robert P. Dick, Li Shang, 2008 .

Graceful Degradation in Algorithm-Based Fault Tolerant Multiprocessor Systems

Niraj K. Jha, Shalini Yajnik, 1997, IEEE Trans. Parallel Distributed Syst..

Hybrid Architectures for Efficient and Secure Face Authentication in Embedded Systems

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

SCANN: Synthesis of Compact and Accurate Neural Networks pdf

Niraj K. Jha, Zeyu Wang, Shayan Hassantabar, 2019, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Synthesis of reversible logic

Niraj K. Jha, Abhinav Agrawal, N. Jha, 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

Algorithm-Based Fault Tolerance for FFT Networks

Niraj K. Jha, Sying-Jyan Wang, 1994, IEEE Trans. Computers.

Diagnosability and Diagnosis of Algorithm-Based Fault-Tolerant Systems

Bapiraju Vinnakota, Niraj K. Jha, N. Jha, 1993, IEEE Trans. Computers.

An Energy-Aware Synthesis Methodology for OS-Driven Multi-Process Embedded Software

Niraj K. Jha, Anand Raghunathan, Tat Kee Tan, 2004, ESA/VLSI.

OpSecure: A Secure Unidirectional Optical Channel for Implantable Medical Devices

Niraj K. Jha, Arsalan Mosenia, N. Jha, 2018, IEEE Transactions on Multi-Scale Computing Systems.

VLSI Design and ASPDAC Technical Program Committee

Dinesh Bhatia, Rajiv V. Joshi, Daniel D. Gajski, 2002 .

Hardware-software co-synthesis of fault-tolerant real-time distributed embedded systems

Niraj K. Jha, Santhanam Srinivasan, 1995, Proceedings of EURO-DAC. European Design Automation Conference.

Behavioral Synthesis of Fault Secure Controller/Datapaths Based on Aliasing Probability Analysis

Niraj K. Jha, Ganesh Lakshminarayana, Anand Raghunathan, 2000, IEEE Trans. Computers.

Pragmatic design of gated-diode FinFET DRAMs

Niraj K. Jha, Ajay N. Bhoj, 2009, 2009 IEEE International Conference on Computer Design.

Input space-adaptive optimization for embedded-software synthesis

Niraj K. Jha, Ganesh Lakshminarayana, Anand Raghunathan, 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Sujit Dey, Niraj K. Jha, Anand Raghunathan, 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

DiabDeep: Pervasive Diabetes Diagnosis Based on Wearable Medical Sensors and Efficient Neural Networks pdf

Niraj K. Jha, Xiaoliang Dai, Hongxu Yin, 2019, IEEE Transactions on Emerging Topics in Computing.

Behavioral Synthesis of Highly Testable Data Paths under the Non-Scan and Partial Scan Environments

Niraj K. Jha, Tien-Chien Lee, Wayne H. Wolf, 1993, 30th ACM/IEEE Design Automation Conference.

Design for hierarchical testability of RTL circuits obtained by behavioral synthesis

Niraj K. Jha, Anand Raghunathan, Indradeep Ghosh, 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Design for Robust Testability

Niraj K. Jha, Sandip Kundu, 1990 .

Synthesis of custom processors based on extensible platforms

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2002, ICCAD 2002.

TAO: regular expression based high-level testability analysis and optimization

Srivaths Ravi, Niraj K. Jha, Ganesh Lakshminarayana, 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

Fault-Tolerant Computing Using a Hybrid Nano-CMOS Architecture

Niraj K. Jha, Martin Rötteler, Srihari Cadambi, 2008, 21st International Conference on VLSI Design (VLSID 2008).

NATURE: a hybrid nanotube/CMOS dynamically reconfigurable architecture

Wei Zhang, Li Shang, Niraj K. Jha, 2006, 2006 43rd ACM/IEEE Design Automation Conference.

A low overhead design for testability and test generation technique for core-based systems

Sujit Dey, Niraj K. Jha, Indradeep Ghosh, 1997, Proceedings International Test Conference 1997.

Leakage power analysis and reduction during behavioral synthesis

Niraj K. Jha, Kamal S. Khouri, N. Jha, 2002, Proceedings 2000 International Conference on Computer Design.

Hardware-Software Co-Design for Test: It's the Last Straw!

Niraj K. Jha, Najmi T. Jarwala, Christos A. Papachristou, 1996, VTS.

Reducing Wire and Energy Overheads of the SMART NoC Using a Setup Request Network

Niraj K. Jha, Xianmin Chen, 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

INVITED: Efficient Synthesis of Compact Deep Neural Networks pdf

Niraj K. Jha, Hongxu Yin, Wenhan Xia, 2020, 2020 57th ACM/IEEE Design Automation Conference (DAC).

Design of Efficient Content Addressable Memories in High-Performance FinFET Technology

Niraj K. Jha, Ajay N. Bhoj, Debajit Bhattacharya, 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Totally self-checking checker designs for Bose-Lin, Bose, and Blaum codes

Niraj K. Jha, 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Die-level leakage power analysis of FinFET circuits considering process variations

Niraj K. Jha, Prateek Mishra, Ajay N. Bhoj, 2010, 2010 11th International Symposium on Quality Electronic Design (ISQED).

Architectures for efficient face authentication in embedded systems

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2006, Proceedings of the Design Automation & Test in Europe Conference.

PowerHerd: dynamic satisfaction of peak power constraints in interconnection networks

Li Shang, Niraj K. Jha, Li-Shiuan Peh, 2003, ICS '03.

MOCSYN: multiobjective core-based single-chip system synthesis

Niraj K. Jha, Robert P. Dick, 1999, DATE '99.

Design of Algorithm-Based Fault Tolerant Systems with In-System Checks

Niraj K. Jha, Shalini Yajnik, N. Jha, 1993, 1993 International Conference on Parallel Processing - ICPP'93.

Enhancing security through hardware-assisted run-time validation of program data properties

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2005, 2005 Third IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'05).

Hardware-software co-synthesis of low power real-time distributed embedded systems with dynamically reconfigurable FPGAs

Li Shang, Niraj K. Jha, N. Jha, 2002, Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design.

Software Architectural Transformations

Niraj K. Jha, Anand Raghunathan, T. K. Tan, 2003, Embedded Software for SoC.

Use of Computation-Unit Integrated Memories in High-Level Synthesis

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Input space adaptive design: a high-level methodology for optimizing energy and performance

Niraj K. Jha, Ganesh Lakshminarayana, Anand Raghunathan, 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Dynamic Binary Instrumentation-Based Framework for Malware Defense

Niraj K. Jha, Anand Raghunathan, Najwa Aaraj, 2008, DIMVA.

Interconnect-aware high-level synthesis for low power

Niraj K. Jha, Lin Zhong, 2002, ICCAD 2002.

MOGAC: a multiobjective genetic algorithm for hardware-software cosynthesis of distributed embedded systems

Niraj K. Jha, Robert P. Dick, 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Computer-aided design algorithms and tools for nanotechnologies

Niraj K. Jha, Rui Zhang, 2006 .

GARNET: A detailed on-chip network model inside a full-system simulator

Niraj K. Jha, Li-Shiuan Peh, Tushar Krishna, 2009, 2009 IEEE International Symposium on Performance Analysis of Systems and Software.

Satisfiability-based Framework for Enabling Side-channel Attacks on Cryptographic Software

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2006, Proceedings of the Design Automation & Test in Europe Conference.

Hardware-Assisted Run-Time Monitoring for Secure Program Execution on Embedded Processors

Srivaths Ravi, Niraj K. Jha, Anand Raghunathan, 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A t-unidirectional error-detecting systematic code

Niraj K. Jha, M. B. Vora, N. Jha, 1988 .

An iterative improvement algorithm for low power data path synthesis

Niraj K. Jha, Anand Raghunathan, N. Jha, 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

Editorial: New Associate Editor Appointments

Niraj K. Jha, 2010, IEEE Trans. Very Large Scale Integr. Syst..

FinFET-Based Power Management for Improved DPA Resistance with Low Overhead

Meng Zhang, Niraj K. Jha, 2011, JETC.

3D vs. 2D Device Simulation of FinFET Logic Gates under PVT Variations

Niraj K. Jha, Sourindra Chaudhuri, N. Jha, 2014, ACM J. Emerg. Technol. Comput. Syst..

Synthesis of fault tolerant architectures for molecular dynamics

Niraj K. Jha, Shalini Yajnik, N. Jha, 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.

Fault detection in DCVS circuits

Niraj K. Jha, B. Vinnakota, 1991, [1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design.

Low-power FinFET circuit synthesis using multiple supply and threshold voltages

Anish Muttreja, Niraj K. Jha, Prateek Mishra, 2009, JETC.

High-Level Power Analysis and Optimization

Sujit Dey, Niraj K. Jha, Anand Raghunathan, 1997 .

A Health Decision Support System for Disease Diagnosis Based on Wearable Medical Sensors and Machine Learning Ensembles

Niraj K. Jha, Hongxu Yin, N. Jha, 2017, IEEE Transactions on Multi-Scale Computing Systems.

Design of multiprocessor systems for concurrent error detection and fault diagnosis

Bapiraju Vinnakota, Niraj K. Jha, 1991, [1991] Digest of Papers. Fault-Tolerant Computing: The Twenty-First International Symposium.

Simultaneous dynamic voltage scaling of processors and communication links in real-time distributed embedded systems

Niraj K. Jha, Jiong Luo, Li-Shiuan Peh, 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

Testing for multiple faults in domino-CMOS logic circuits

Niraj K. Jha, 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

QLib: Quantum module library

Niraj K. Jha, Amlan Chakrabarti, Chia-Chun Lin, 2014, ACM J. Emerg. Technol. Comput. Syst..

A Test Generation Framework for Quantum Cellular Automata Circuits

Niraj K. Jha, Loganathan Lingappan, Pallav Gupta, 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

SHARKS: Smart Hacking Approaches for RisK Scanning in Internet-of-Things and Cyber-Physical Systems based on Machine Learning pdf

Niraj K. Jha, Najwa Aaraj, Tanujay Saha, 2021, ArXiv.

MHDeep: Mental Health Disorder Detection System based on Body-Area and Deep Neural Networks pdf

Niraj K. Jha, Hongxu Yin, Shayan Hassantabar, 2021, ArXiv.

CovidDeep: SARS-CoV-2/COVID-19 Test Based on Wearable Medical Sensors and Efficient Neural Networks

Niraj K. Jha, Kenza Hamidouche, Shayan Hassantabar, 2021, IEEE Transactions on Consumer Electronics.

Fast Design Space Exploration of Nonlinear Systems: Part I pdf

Niraj K. Jha, Brendan Englot, Sanjai Narain, 2021, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

GRAVITAS: Graphical Reticulated Attack Vectors for Internet-of-Things Aggregate Security pdf

Niraj K. Jha, Tanujay Saha, Jacob Brown, 2021, IEEE Transactions on Emerging Topics in Computing.

Convolutional Autoencoder-Based Transfer Learning for Multi-Task Image Inferences

Naveen Verma, Niraj K. Jha, Jie Lucy Lu, 2021 .

Machine Learning Assisted Security Analysis of 5G-Network-Connected Systems pdf

Niraj K. Jha, Najwa Aaraj, Tanujay Saha, 2021, IEEE Transactions on Emerging Topics in Computing.

Towards Execution-Efficient LSTMs via Hardware-Guided Grow-and-Prune Paradigm

Niraj K. Jha, Weifeng Zhang, Yingmin Li, 2022, IEEE Transactions on Emerging Topics in Computing.

SYSTEMATIC CODE FOR DETECTING T-UNIDIRECTIONAL ERRORS.

Niraj K. Jha, Mahendra B. Vora, 1987 .

Multi-sensor Targets Data Association and Track Fusion Based on Novel AWFCM

Niraj K. Jha, Rui Guo, N. Jha, 2009 .

Techniques for efficiently implementing totally self-checking checkers in MOS te

Niraj K. Jha, J. A. Abraham, 1987 .

2018 IEEE International Conference on Consumer Electronics (ICCE)

Niraj K. Jha, Swarup Bhunia, Koji Nakao, 2018 .

Garnet : A Detailed Interconnect Model Inside a Full-System Simulation Framework

Niraj K. Jha, Li-Shiuan Peh, Niket Agarwal, .

Easily testable DCVS multiplier

Niraj K. Jha, A. Takach, 1990, IEEE International Symposium on Circuits and Systems.

Nanoelectronic circuit design

Niraj K. Jha, Deming Chen, Niraj K. Jha, 2011 .

Threshold network synthesis and optimization and its application to nanotechnologies

Niraj K. Jha, Lin Zhong, Rui Zhang, 2005 .

Testing of differential cascode voltage switch one-count generators

Niraj K. Jha, 1990 .

Switching and Finite Automata Theory: Finite-state recognizers

Niraj K. Jha, Zvi Kohavi, 2009 .