S. Hijiya

A wafer-scale 170000-gate FFT processor with built-in test circuits

G. Goto, K. Yamashita, A. Kanasugi, 1988 .

A wafer-scale FFT processor featuring a repeatable building block

G. Goto, Akinori Kanasugi, K. Yamashita, 1989, [1989] Proceedings International Conference on Wafer Scale Integration.

Fabrication of Double-Gate Thin-Film SOI MOSFETs Using Wafer Bonding and Polishing

Tetsu Tanaka, S. Ando, Yoshihiro Arimoto, 1991 .

Analysis of p/sup +/ poly Si double-gate thin-film SOI MOSFETs

Tetsu Tanaka, S. Ando, Hiroshi Horie, 1991, International Electron Devices Meeting 1991 [Technical Digest].

A capacitance coupled bit line cell for Mb level DRAMs

T. Nakamura, T. Yabu, S. Hijiya, 1984, 1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

A Capacitance-Coupled Bit Line Cell

T. Nakamura, S. Ando, T. Yabu, 1985, IEEE Journal of Solid-State Circuits.

Low-voltage alterable EAROM cells with nitride-barrier avalanche-injection MIS (NAMIS)

M. Shinoda, S. Hijiya, S. Hijiya, 1979, IEEE Transactions on Electron Devices.