J. S. Neely

CPAM: a common power analysis methodology for high-performance VLSI design

H. H. Chen, J. S. Neely, S. G. Walker, 2000, IEEE 9th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.00TH8524).

Interconnect and circuit modeling techniques for full-chip power supply noise analysis

J. S. Neely, H. H. Chen, J. Neely, 1998 .

A room temperature 0.1 /spl mu/m CMOS on SOI

Tak H. Ning, James D. Warnock, R. L. Franch, 1994 .