Junichi Miyakoshi

发表

A Two-Port SRAM for Real-Time Video Processor Saving 53% of Bitline Power with Majority Logic and Data-Bit Reordering

Hidehiro Fujiwara, Koji Nii, Junichi Miyakoshi, 2006, ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design.

Novel Video Memory Reduces 45% of Bitline Power Using Majority Logic and Data-Bit Reordering

Masahiko Yoshimoto, Hidehiro Fujiwara, Koji Nii, 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A Power- and Area-Efficient SRAM Core Architecture for Super-Parallel Video Processing

Masahiko Yoshimoto, Masaki Hamamoto, Junichi Miyakoshi, 2006, 2006 IFIP International Conference on Very Large Scale Integration.

PAPER Special Section on VLSI Design and CAD Algorithms A 0.3-V Operating, Vth-Variation-Tolerant SRAM under DVS Environment for Memory-Rich SoC in 90-nm Technology Era and Beyond

Masahiko Yoshimoto, Hidehiro Fujiwara, Junichi Miyakoshi, 2006 .

A Low-Power Systolic Array Architecture for Block-Matching Motion Estimation

Masahiko Yoshimoto, Junichi Miyakoshi, Yuichiro Murachi, 2005, IEICE Trans. Electron..

A Power- and Area-Efficient SRAM Core Architecture with Segmentation-Free and Horizontal/Vertical Accessibility for Super-Parallel Video Processing

Masahiko Yoshimoto, Junichi Miyakoshi, Yuichiro Murachi, 2006, IEICE Trans. Electron..

A 95mW MPEG2 MP@HL motion estimation processor core for portable high resolution video application

Masahiko Yoshimoto, Junichi Miyakoshi, Yuichiro Murachi, 2005, VLSIC 2005.

A sub 100 mW H.264/AVC MP@L4.1 integer-pel motion estimation processor VLSI for MBAFF encoding

Masahiko Yoshimoto, Masaki Hamamoto, Junichi Miyakoshi, 2008, 2008 IEEE International Symposium on Circuits and Systems.

VLSI Architecture Study of a Real-Time Scalable Optical Flow Processor for Video Segmentation

Masahiko Yoshimoto, Junichi Miyakoshi, Ryo Yamamoto, 2006, IEICE Trans. Electron..

C-12-14 An MPEG2 MP@HL Motion Estimation Algorithm Optimized for Low Power VLSI (2) : Arithmetic and Control Simplification

Masahiko Yoshimoto, Junichi Miyakoshi, Yuichiro Murachi, 2004 .

An Ultra Low Power Motion Estimation Processor for MPEG2 HDTV Resolution Video

Masahiko Yoshimoto, Junichi Miyakoshi, Mikio Yagi, 2003 .

A 95mW MPEG2 MP@HL motion estimation processor core for portable high resolution video application

Masahiko Yoshimoto, Junichi Miyakoshi, Yuichiro Murachi, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005..

A 0.3-V Operating, Vth-Variation-Tolerant SRAM under DVS Environment for Memory-Rich SoC in 90-nm Technology Era and Beyond

Masahiko Yoshimoto, Hidehiro Fujiwara, Koji Nii, 2006, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Size-adaptive hepatocellular carcinoma detection from 3D CT images based on the level set method

Ryo Kurazume, Junichi Miyakoshi, Kazuki Matsuzaki, 2012, Medical Imaging.

An 80-1 WH 264 Baseline-ProfileMotionEstimation Processor Core

Masahiko Yoshimoto, Masaki Hamamoto, Junichi Miyakoshi, 2006 .

False-positive reduction of liver tumor detection using ensemble learning method

Junichi Miyakoshi, Atsushi Miyamoto, Kazuki Matsuzaki, 2013, Medical Imaging.

A VGA 30-fps Realtime Optical-Flow Processor Core for Moving Picture Recognition

Masahiko Yoshimoto, Junichi Miyakoshi, Yuichiro Murachi, 2008, IEICE Trans. Electron..

A Sub 100 mW H.264 MP@L4.1 Integer-Pel Motion Estimation Processor Core for MBAFF Encoding with Reconfigurable Ring-Connected Systolic Array and Segmentation-Free, Rectangle-Access Search-Window Buffer

Masahiko Yoshimoto, Masaki Hamamoto, Junichi Miyakoshi, 2008, IEICE Trans. Electron..

VLSI-Oriented Motion Estimation Using a Steepest Descent Method in Mobile Video Coding

Masahiko Yoshimoto, Junichi Miyakoshi, Hideo Hashimoto, 2004 .

An Architecture Study of Scalable Optical-Flow Processor for Real-Time Video Segmentation

Masahiko Yoshimoto, Junichi Miyakoshi, Hiroshi Kawaguchi, 2004 .

Metastatic liver tumor detection from 3D CT images using a level set algorithm with liver-edge term

Junichi Miyakoshi, Kazuki Matsuzaki, Shuntaro Yui, 2012, Medical Imaging.

A 45nm 37.3GOPS/W heterogeneous multi-core SoC

Junichi Miyakoshi, Hironori Kasahara, Tetsuya Yamada, 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

An H.264/AVC MP@L4.1 quarter-pel motion estimation processor VLSI for real-time MBAFF encoding

Masahiko Yoshimoto, Masaki Hamamoto, Junichi Miyakoshi, 2008, 2008 15th IEEE International Conference on Electronics, Circuits and Systems.

A Sub-mW H.264 Baseline-Profile Motion Estimation Processor Core with a VLSI-Oriented Block Partitioning Strategy and SIMD/Systolic-Array Architecture

Masahiko Yoshimoto, Masaki Hamamoto, Junichi Miyakoshi, 2006, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A sub-mW MPEG-4 motion estimation processor core for mobile video application

Masahiko Yoshimoto, Junichi Miyakoshi, Hideo Hashimoto, 2004, IEEE Journal of Solid-State Circuits.

A 45-nm 37.3 GOPS/W Heterogeneous Multi-Core SOC with 16/32 Bit Instruction-Set General-Purpose Core

Junichi Miyakoshi, Hironori Kasahara, Tetsuya Yamada, 2011, IEICE Trans. Electron..

Social Co-OS: Cyber-Human Social Co-Operating System pdf

Junichi Miyakoshi, Yasuyuki Kudo, Ryuji Mine, 2021, ArXiv.