Hiroshi Kawaguchi

发表

A Two-Port SRAM for Real-Time Video Processor Saving 53% of Bitline Power with Majority Logic and Data-Bit Reordering

Hidehiro Fujiwara, Koji Nii, Junichi Miyakoshi, 2006, ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design.

Radiation-Induced Soft Errors

Shusuke Yoshimoto, Hiroshi Kawaguchi, Yukio Mitsuyama, 2018, VLSI Design and Test for Systems Dependability.

Low-power block-level instantaneous comparison 7T SRAM for dual modular redundancy

Yuki Kagiyama, Shunsuke Okumura, Koji Yanagida, 2011, 2011 IEEE Custom Integrated Circuits Conference (CICC).

Non-contact Instantaneous Heart Rate Monitoring Using Microwave Doppler Sensor and Time-Frequency Domain Analysis

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2016, 2016 IEEE 16th International Conference on Bioinformatics and Bioengineering (BIBE).

Signal contributions to heavily diffusion-weighted functional magnetic resonance imaging investigated with multi-SE-EPI acquisitions

Hiroshi Kawaguchi, Iwao Kanno, Jeff Kershaw, 2014, NeuroImage.

A 15-μA metabolic equivalents monitoring system using adaptive acceleration sampling and normally off computing

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2016, 2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS).

A 54-mw 3×-real-time 60-kword continuous speech recognition processor VLSI

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2014, IEICE Electron. Express.

A 75-variable MIQP solver processor for real-time autonomous robot control

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2011, 2011 IEEE/SICE International Symposium on System Integration (SII).

Frequency-voltage cooperative CPU power control: A design rule and its application by feedback prediction

Hiroshi Kawaguchi, Toshiyuki Aritsuka, Takayasu Sakurai, 2005, Systems and Computers in Japan.

Architectural Study of HOG Feature Extraction Processor for Real-Time Object Detection

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2012, 2012 IEEE Workshop on Signal Processing Systems.

A physical unclonable function chip exploiting load transistors' variation in SRAM bitcells

Shunsuke Okumura, Shusuke Yoshimoto, Masahiko Yoshimoto, 2013, 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC).

Noise-tolerant instantaneous heart rate and R-peak detection using short-term autocorrelation for wearable healthcare systems

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2013, 2013 35th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC).

An LSI for V/sub DD/-hopping and MPEG4 system based on the chip

Hiroshi Kawaguchi, Seongsoo Lee, Takayasu Sakurai, 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

Estimating metabolic equivalents for activities in daily life using acceleration and heart rate in wearable devices

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2018, Biomedical engineering online.

Low-Power Low-Leakage FPGA Design Using Zigzag Power Gating, Dual-VTH/VDD and Micro-VDD-Hopping

Hiroshi Kawaguchi, Takayasu Sakurai, Canh Quang Tran, 2006, IEICE Trans. Electron..

A Power-Variation Model for Sensor Node and the Impact against Life Time of Wireless Sensor Networks

Masahiko Yoshimoto, Hiroshi Kawaguchi, Chikara Ohta, 2006, 2006 First International Conference on Communications and Electronics.

Back-propagation Learning Algorithm for Non-destructive Testing by Thermal Imager

Fumio Kojima, Hiroshi Kawaguchi, 1993 .

A Second-Order All-Digital TDC with Low-Jitter Frequency Shift Oscillators and Dynamic Flipflops

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2013, IEICE Trans. Electron..

Low-power hardware implementation of noise tolerant heart rate extractor for a wearable monitoring system

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2013, 13th IEEE International Conference on BioInformatics and BioEngineering.

Failure Modes and Effects Analysis Using Virtual Prototyping System with Microcontroller Model for Automotive Control System

Yohei Nakata, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2013 .

A 60-dB image rejection filter using Δ-Σ modulation and frequency shifting

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2009, 2009 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing.

A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM using low-power disturb mitigation technique

Shunsuke Okumura, Shusuke Yoshimoto, Masahiko Yoshimoto, 2013, 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC).

Novel Video Memory Reduces 45% of Bitline Power Using Majority Logic and Data-Bit Reordering

Masahiko Yoshimoto, Hidehiro Fujiwara, Koji Nii, 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Live demonstration: Intelligent ubiquitous sensor network for sound acquisition

Masahiko Yoshimoto, Hiroshi Kawaguchi, Hiroki Noguchi, 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

Power and Memory Bandwidth Reduction of an H.264/AVC HDTV Decoder LSI with Elastic Pipeline Architecture

Masahiko Yoshimoto, Hiroshi Kawaguchi, Kentaro Kawakami, 2007, 2007 Asia and South Pacific Design Automation Conference.

Dynamic leakage cut-off scheme for low-voltage SRAM's

Hiroshi Kawaguchi, Takayasu Sakurai, Y. Itaka, 1998, 1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215).

Data-Intensive Sound Acquisition System with Large-scale Microphone Array

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2011, J. Inf. Process..

An soft error propagation analysis considering logical masking effect on re-convergent path

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2016, 2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS).

Intelligent ubiquitous sensor network for sound acquisition

Masahiko Yoshimoto, Hiroshi Kawaguchi, Hiroki Noguchi, 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

A 284-µW 1.85-GHz 20-phase oscillator using transfer gate phase couplers

Masahiko Yoshimoto, Hiroshi Kawaguchi, Takashi Takeuchi, 2010, 2010 Asia-Pacific Microwave Conference.

Low-energy block-level instantaneous comparison 7T SRAM for dual modular redundancy

Yuki Kagiyama, Shunsuke Okumura, Koji Yanagida, 2012, IEICE Electron. Express.

A Power- and Area-Efficient SRAM Core Architecture for Super-Parallel Video Processing

Masahiko Yoshimoto, Masaki Hamamoto, Junichi Miyakoshi, 2006, 2006 IFIP International Conference on Very Large Scale Integration.

SRAM Enabling Low-Energy Instantaneous Block Copy and Its Application to Transactional Memory

Yuki Kagiyama, Shunsuke Okumura, Shusuke Yoshimoto, 2011 .

Adaptive Learning Rate Adjustment with Short-Term Pre-Training in Data-Parallel Deep Learning

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2018, 2018 IEEE International Workshop on Signal Processing Systems (SiPS).

Design Choice in 45-nm Dual-Port SRAM - 8T, 10T Single End, and 10T Differential

Shunsuke Okumura, Masahiko Yoshimoto, Hidehiro Fujiwara, 2011, IPSJ Trans. Syst. LSI Des. Methodol..

A ferroelectric-based non-volatile flip-flop for wearable healthcare systems

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2015, 2015 15th Non-Volatile Memory Technology Symposium (NVMTS).

Low-power CMOS design through VTH control and low-swing circuits

Hiroshi Kawaguchi, Tadahiro Kuroda, Takayasu Sakurai, 1997, ISLPED '97.

Low-power control techniques for silicon and organic circuits with array structures

Hiroshi Kawaguchi, 2009, 2009 IEEE Control Applications, (CCA) & Intelligent Control, (ISIC).

A 40-nm resilient cache memory for dynamic variation tolerance with bit-enhancing memory and on-chip diagnosis structures delivering ×91 failure rate improvement

Hiroyuki Kawai, Shunsuke Okumura, Yohei Nakata, 2014, Fifteenth International Symposium on Quality Electronic Design.

AN ULTRA-LOW-POWERVAD HARDWAREIMPLEMENTATION FOR INTELLIGENT UBIQUITOUS SENSORNETWORKS

Hiroshi Kawaguchi, Hiroki Noguchi, Tomoya Takagi, 2009 .

A 40-nm 256-Kb Sub-10 pJ/Access 8t SRAM with read bitline amplitude limiting (RBAL) scheme

Shunsuke Okumura, Shusuke Yoshimoto, Masahiko Yoshimoto, 2012, ISLPED '12.

0.45-V operating Vt-variation tolerant 9T/18T dual-port SRAM

Shunsuke Okumura, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2011, 2011 12th International Symposium on Quality Electronic Design.

An ultra-low-power VAD hardware implementation for intelligent ubiquitous sensor networks

Masahiko Yoshimoto, Hiroshi Kawaguchi, Hiroki Noguchi, 2009, 2009 IEEE Workshop on Signal Processing Systems.

Low-Power SRAM in 28-nm FD-SOI for Image Processor

Shusuke Yoshimoto, Shintaro Izumi, Masahiko Yoshimoto, 2014 .

A Power- and Area-Efficient SRAM Core Architecture with Segmentation-Free and Horizontal/Vertical Accessibility for Super-Parallel Video Processing

Masahiko Yoshimoto, Junichi Miyakoshi, Yuichiro Murachi, 2006, IEICE Trans. Electron..

A 34.7-mW quad-core MIQP solver processor for robot control

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2010, IEEE Custom Integrated Circuits Conference 2010.

A Low-Power Multi-Phase Oscillator with Transfer Gate Phase Coupler Enabling Even-Numbered Phase Output

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2011, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

PAPER Special Section on Circuits and Design Techniques for Advanced Large Scale Integration VLSI Architecture of GMM Processing and Viterbi Decoder for 60,000-Word Real-Time Continuous Speech Recognition ∗

Masahiko Yoshimoto, Hiroshi Kawaguchi, Kazuo Miura, 2011 .

A swallowable sensing device platform with wireless power feeding and chemical reaction actuator

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2017, 2017 39th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC).

Reconfiguring Cache Associativity: Adaptive Cache Design for Wide-Range Reliable Low-Voltage Operation Using 7T/14T SRAM

Shunsuke Okumura, Yohei Nakata, Masahiko Yoshimoto, 2013, IEICE Trans. Electron..

A 0.15-µm FD-SOI Substrate Bias Control SRAM with Inter-Die Variability Compensation Scheme

Shunsuke Okumura, Shusuke Yoshimoto, Masahiko Yoshimoto, 2012, IEICE Trans. Electron..

A metabolic equivalents estimation algorithm using triaxial accelerometer and adaptive sampling for wearable devices

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2017, 2017 IEEE Life Sciences Conference (LSC).

An FPGA Implementation of a HOG-based Object Detection Processor

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2013, IPSJ Trans. Syst. LSI Des. Methodol..

Error Propagation Analysis for Single Event Upset considering Masking Effects on Re-Convergent Path

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2016, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Adaptive noise cancellation method for capacitively coupled ECG sensor using single insulated electrode

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2016, 2016 IEEE Biomedical Circuits and Systems Conference (BioCAS).

A Real-time Scalable Object Detection System using Low-power HOG Accelerator VLSI

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2014, J. Signal Process. Syst..

0.5-V operation variation-aware word-enhancing cache architecture using 7T/14T hybrid SRAM

Shunsuke Okumura, Yohei Nakata, Masahiko Yoshimoto, 2010, 2010 ACM/IEEE International Symposium on Low-Power Electronics and Design (ISLPED).

A 40 nm 144 mW VLSI processor for realtime 60 kWord continuous speech recognition

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2011, 2011 IEEE Custom Integrated Circuits Conference (CICC).

Trends of On-Chip Interconnects in Deep Sub-Micron VLSI

Hiroshi Kawaguchi, Takayasu Sakurai, Kenichi Inagaki, 2006, IEICE Trans. Electron..

Bit error and soft error hardenable 7T/14T SRAM with 150-nm FD-SOI process

Shunsuke Okumura, Shusuke Yoshimoto, Hiroshi Kawaguchi, 2011, 2011 International Reliability Physics Symposium.

Multiple-Bit-Upset and Single-Bit-Upset Resilient 8T SRAM Bitcell Layout with Divided Wordline Structure

Shunsuke Okumura, Shusuke Yoshimoto, Masahiko Yoshimoto, 2012 .

Hardware Implementation of Autoregressive Model Estimation Using Burg’s Method for Low-Energy Spectral Analysis

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2018, 2018 IEEE International Workshop on Signal Processing Systems (SiPS).

Frequency–voltage cooperative CPU power control: A design rule and its application by feedback prediction

Hiroshi Kawaguchi, Toshiyuki Aritsuka, Takayasu Sakurai, 2005 .

Subthreshold-leakage suppressed switched capacitor circuit based on super cut-off CMOS (SCCMOS)

Hiroshi Kawaguchi, Kouichi Kanda, Takayasu Sakurai, 2005, 2005 IEEE International Symposium on Circuits and Systems.

More than two orders of magnitude leakage current reduction in look-up table for FPGAs

Hiroshi Kawaguchi, Takayasu Sakurai, Canh Quang Tran, 2005, 2005 IEEE International Symposium on Circuits and Systems.

256-KB associativity-reconfigurable cache with 7T/14T SRAM for aggressive DVS down to 0.57 V

Shunsuke Okumura, Yohei Nakata, Masahiko Yoshimoto, 2011, 2011 18th IEEE International Conference on Electronics, Circuits, and Systems.

Area Comparison between 6T and 8T SRAM Cells in Dual-Vdd Scheme and DVS Scheme

Masahiko Yoshimoto, Hidehiro Fujiwara, Koji Nii, 2007, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A 61-dB SNDR 700 µm2 second-order all-digital TDC with low-jitter frequency shift oscillators and dynamic flipflops

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2012, 2012 Symposium on VLSI Circuits (VLSIC).

IsochronousMAC usingLong-Wave Standard Time Code forWirelessSensorNetworks

Masahiko Yoshimoto, Hiroshi Kawaguchi, Chikara Ohta, 2006 .

Sampling Rate Reduction for Wearable Heart Rate Variability Monitoring

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2018, 2018 IEEE International Symposium on Circuits and Systems (ISCAS).

Quality of a Bit (QoB): A New Concept in Dependable SRAM

Shunsuke Okumura, Masahiko Yoshimoto, Yasuhiro Morita, 2008, ISQED 2008.

A 6T-4C shadow memory using plate line and word line boosting

Koji Yanagida, Shusuke Yoshimoto, Shintaro Izumi, 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).

Counter-Based Broadcasting with Hop Count Aware Random Assessment Delay Extension for Wireless Sensor Networks

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2008, IEICE Trans. Commun..

A 40-nm 640-µm2 45-dB opampless all-digital second-order MASH ΔΣ ADC

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2011, 2011 IEEE International Symposium of Circuits and Systems (ISCAS).

An I/O-Sized ADC with Second-Order TDC and MOM Capacitor Voltage-to-Time Converter

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2015, IEICE Trans. Electron..

Soft-Error Resilient and Margin-Enhanced N-P Reversed 6T SRAM Bitcell

Shusuke Yoshimoto, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2014, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Cooperative voltage scaling (CVS) between OS and applications for low-power real-time systems

Hiroshi Kawaguchi, Takayasu Sakurai, Youngsoo Shin, 2001, Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169).

A Dependable SRAM with 7T/14T Memory Cells

Shunsuke Okumura, Masahiko Yoshimoto, Hidehiro Fujiwara, 2009, IEICE Trans. Electron..

Normally-off technologies for healthcare appliance

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2014, 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC).

A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM Using Low-Energy Disturb Mitigation Scheme

Shunsuke Okumura, Shusuke Yoshimoto, Masahiko Yoshimoto, 2012, IEICE Trans. Electron..

An Opampless Second-Order MASH ΔΣ ADC with Using Gated Ring Oscillator Time-to-Digital Converter

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2013, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A 28-nm FD-SOI 8T Dual-Port SRAM for Low-Energy Image Processor With Selective Sourceline Drive Scheme

Shusuke Yoshimoto, Shintaro Izumi, Masahiko Yoshimoto, 2019, IEEE Transactions on Circuits and Systems I: Regular Papers.

A 58-µW single-chip sensor node processor using synchronous MAC protocol

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2009, 2009 Symposium on VLSI Circuits.

A sub 100 mW H.264/AVC MP@L4.1 integer-pel motion estimation processor VLSI for MBAFF encoding

Masahiko Yoshimoto, Masaki Hamamoto, Junichi Miyakoshi, 2008, 2008 IEEE International Symposium on Circuits and Systems.

Multiple-Cell-Upset Tolerant 6T SRAM Using NMOS-Centered Cell Layout

Shunsuke Okumura, Shusuke Yoshimoto, Masahiko Yoshimoto, 2013, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Analysis of Soft Error Propagation Considering Masking Effects on Re-Convergent Path

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2015, 2015 IEEE 24th Asian Test Symposium (ATS).

A 298-fJ/writecycle 650-fJ/readcycle 8T three-port SRAM in 28-nm FD-SOI process technology for image processor

Shusuke Yoshimoto, Shintaro Izumi, Masahiko Yoshimoto, 2015, 2015 IEEE Custom Integrated Circuits Conference (CICC).

Data Transmission of Computer Network using Satellite and Terrestrial Network

Hiroshi Kawaguchi, Manabu Nakagawa, Youichi Hashimoto, 1996 .

Scalable parallel processing for H.264 encoding application to multi/many-core processor

Masahiko Yoshimoto, Hiroshi Kawaguchi, Yukihiro Takeuchi, 2010, 2010 International Conference on Intelligent Control and Information Processing.

Cross-Layer Design for Low-Power Wireless Sensor Node Using Wave Clock

Masahiko Yoshimoto, Hiroshi Kawaguchi, Chikara Ohta, 2008, IEICE Trans. Commun..

A 7T/14T Dependable SRAM and its Array Structure to Avoid Half Selection

Shunsuke Okumura, Masahiko Yoshimoto, Hidehiro Fujiwara, 2009, 2009 22nd International Conference on VLSI Design.

Row-by-Row Dynamic Source-Line Voltage Control (RRDSV) Scheme for Two Orders of Magnitude Leakage Current Reduction of Sub-1-V-VDD SRAM's

Hiroshi Kawaguchi, Kouichi Kanda, Takayasu Sakurai, 2005, IEICE Trans. Electron..

Observation of one-fifth-of-a-clock wake-up time of power-gated circuit

Hiroshi Kawaguchi, Takayasu Sakurai, Canh Quang Tran, 2004, Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571).

Fast and Low-Memory-Bandwidth Architecture of SIFT Descriptor Generation with Scalability on Speed and Accuracy for VGA Video

Masahiko Yoshimoto, Hiroshi Kawaguchi, Hiroki Noguchi, 2010, 2010 International Conference on Field Programmable Logic and Applications.

Simple Waveform Model of Inductive Interconnects by Delayed Quadratic Transfer Function with Application to Scaling Trend of Inductive Effects in VLSI's

Hiroshi Kawaguchi, Takayasu Sakurai, Kenichi Inagaki, 2006, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A 128-bit chip identification generating scheme exploiting SRAM bitcells with failure rate of 4.45 × 10−19

Shunsuke Okumura, Shusuke Yoshimoto, Masahiko Yoshimoto, 2011, 2011 Proceedings of the ESSCIRC (ESSCIRC).

Parallel-processing VLSI architecture for mixed integer linear programming

Masahiko Yoshimoto, Hiroshi Kawaguchi, Hiroki Noguchi, 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

"E-correctness" of a set of "computation processes"

Hiroshi Kawaguchi, Kazuhide Sugawara, Teruyasu Nishizawa, 1978, Mathematical Studies of Information Processing.

A designmethodology of chip-to-chip wirelesspower transmission system

Hiroshi Kawaguchi, 2007 .

Non-contact biometric identification and authentication using microwave Doppler sensor

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2017, 2017 IEEE Biomedical Circuits and Systems Conference (BioCAS).

Parallelized viterbi processor for 5, 000-word large-vocabulary real-time continuous speech recognition FPGA system

Masahiko Yoshimoto, Hiroshi Kawaguchi, Kazuo Miura, 2009, INTERSPEECH.

Low-power metabolic equivalents estimation algorithm using adaptive acceleration sampling

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2016, 2016 38th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC).

DELAYED WEIGHT UPDATE FOR FASTER CONVERGENCE IN DATA-PARALLEL DEEP LEARNING

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2018, 2018 IEEE Global Conference on Signal and Information Processing (GlobalSIP).

A Low-Power Multi Resolution Spectrum Sensing (MRSS) Architecture for a Wireless Sensor Network with Cognitive Radio

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2010, 2010 Fourth International Conference on Sensor Technologies and Applications.

Normally Off ECG SoC With Non-Volatile MCU and Noise Tolerant Heartbeat Detector

Hiroshi Nakajima, Shusuke Yoshimoto, Shintaro Izumi, 2015, IEEE Transactions on Biomedical Circuits and Systems.

A negative-resistance sense amplifier for low-voltage operating STT-MRAM

Koji Yanagida, Shusuke Yoshimoto, Shintaro Izumi, 2015, The 20th Asia and South Pacific Design Automation Conference.

Data Aggregation Protocol for Multiple Sound Sources Acquisition with Microphone Array Network

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2011, 2011 Proceedings of 20th International Conference on Computer Communications and Networks (ICCCN).

A 38 μA wearable biosignal monitoring system with near field communication

Hiroshi Nakajima, Shintaro Izumi, Masahiko Yoshimoto, 2013, 2013 IEEE 11th International New Circuits and Systems Conference (NEWCAS).

An impression-word-giving system for images based on colors

Hiroshi Kawaguchi, Kazuhiko Shiranita, Kenichiro Hayashi, 2003 .

FP 12.4: A CMOS Scheme for 0.5V Supply Voltage with Pico-Ampere Standby Current

Hiroshi Kawaguchi, Takayasu Sakurai, Koichi Nose, 1998 .

Layer Skip Learning using LARS variables for 39% Faster Conversion Time and Lower Bandwidth

Masahiko Yoshimoto, Hiroshi Kawaguchi, Haruki Mori, 2018, 2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS).

A 58-µW Single-Chip Sensor Node Processor with Communication Centric Design

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2010, IEICE Trans. Electron..

A low power 6T-4C non-volatile memory using charge sharing and non-precharge techniques

Koji Yanagida, Shusuke Yoshimoto, Shintaro Izumi, 2015, 2015 IEEE International Symposium on Circuits and Systems (ISCAS).

A 0.56-V 128kb 10T SRAM using column line assist (CLA) scheme

Shunsuke Okumura, Shusuke Yoshimoto, Masahiko Yoshimoto, 2009, 2009 10th International Symposium on Quality Electronic Design.

A 10T Non-precharge Two-Port SRAM Reducing Readout Power for Video Processing

Shunsuke Okumura, Masahiko Yoshimoto, Hidehiro Fujiwara, 2008, IEICE Trans. Electron..

Data Transmission Scheduling Based on RTS/CTS Exchange for Periodic Data Gathering Sensor Networks

Masahiko Yoshimoto, Hiroshi Kawaguchi, Chikara Ohta, 2007, IEICE Trans. Commun..

An accurate soft error propagation analysis technique considering temporal masking disablement

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2015, 2015 IEEE 21st International On-Line Testing Symposium (IOLTS).

A 0.3-V Operating, Vth-Variation-Tolerant SRAM under DVS Environment for Memory-Rich SoC in 90-nm Technology Era and Beyond

Masahiko Yoshimoto, Hidehiro Fujiwara, Koji Nii, 2006, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Model-based fault injection for failure effect analysis — Evaluation of dependable SRAM for vehicle control units

Shunsuke Okumura, Yohei Nakata, Masahiko Yoshimoto, 2011, 2011 IEEE/IFIP 41st International Conference on Dependable Systems and Networks Workshops (DSN-W).

A Self-Alignment Row-by-Row Variable-VDD Scheme Reducing 90% of Active-Leakage Power in SRAM's

Hiroshi Kawaguchi, Takayasu Sakurai, Fayez Robert Saliba, 2007, IEICE Trans. Electron..

Model-Based Fault Injection for Failure Effect Analysis

Shunsuke Okumura, Yohei Nakata, Masahiko Yoshimoto, 2011 .

A Low-Latency DMR Architecture with Fast Checkpoint Recovery Scheme

Yohei Nakata, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2015 .

A 128-bit Chip Identification Generating Scheme Exploiting Load Transistors' Variation in SRAM Bitcells

Shunsuke Okumura, Shusuke Yoshimoto, Masahiko Yoshimoto, 2012, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Leakage-suppressed clock-gating circuit with Zigzag Super Cut-off CMOS (ZSCCMOS) for leakage-dominant sub-70-nm and sub-1-V-V/sub DD/ LSIs

Hiroshi Kawaguchi, Takayasu Sakurai, Kyeong-Sik Min, 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Multimodal cardiovascular information monitor using piezoelectric transducers for wearable healthcare

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2017, 2017 IEEE International Workshop on Signal Processing Systems (SiPS).

A 40-NM 54-MW 3×-real-time VLSI processor for 60-kWord continuous speech recognition

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2013, SiPS 2013 Proceedings.

An 80-1 WH 264 Baseline-ProfileMotionEstimation Processor Core

Masahiko Yoshimoto, Masaki Hamamoto, Junichi Miyakoshi, 2006 .

Handsfree Voice Interface for Home Network Service Using a Microphone Array Network

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2012, 2012 Third International Conference on Networking and Computing.

7T SRAM enabling low-energy simultaneous block copy

Shunsuke Okumura, Shusuke Yoshimoto, Yohei Nakata, 2010, IEEE Custom Integrated Circuits Conference 2010.

A 11.3-µA Physical Activity Monitoring System Using Acceleration and Heart Rate

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2018, IEICE transactions on electronics.

A 40-nm 8T SRAM with selective source line control of read bitlines and address preset structure

Shusuke Yoshimoto, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2013, Proceedings of the IEEE 2013 Custom Integrated Circuits Conference.

Large displacement haptic stimulus actuator using piezoelectric pump for wearable devices

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2015, Annual International Conference of the IEEE Engineering in Medicine and Biology Society.

Quality of a Bit (QoB): A New Concept in Dependable SRAM

Shunsuke Okumura, Masahiko Yoshimoto, Hidehiro Fujiwara, 2008, 9th International Symposium on Quality Electronic Design (isqed 2008).

A 40-nm 256-Kb 0.6-V operation half-select resilient 8T SRAM with sequential writing technique enabling 367-mV VDDmin reduction

Shunsuke Okumura, Shusuke Yoshimoto, Masahiko Yoshimoto, 2012, Thirteenth International Symposium on Quality Electronic Design (ISQED).

A layer-block-wise pipeline for memory and bandwidth reduction in distributed deep learning

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2017, 2017 IEEE 27th International Workshop on Machine Learning for Signal Processing (MLSP).

An low-energy 8T dual-port SRAM for image processor with selective sourceline drive scheme in 28-nm FD-SOI process technology

Shusuke Yoshimoto, Shintaro Izumi, Masahiko Yoshimoto, 2016, 2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS).

A sub-100-milliwatt dual-core HOG accelerator VLSI for real-time multiple object detection

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2013, 2013 IEEE International Conference on Acoustics, Speech and Signal Processing.

FPGA implementation of object recognition processor for HDTV resolution video using sparse FIND feature

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2017, 2017 IEEE International Workshop on Signal Processing Systems (SiPS).

A 28-nm 484-fJ/writecycle 650-fJ/readcycle 8T Three-Port FD-SOI SRAM for Image Processor

Shusuke Yoshimoto, Shintaro Izumi, Masahiko Yoshimoto, 2016, IEICE Trans. Electron..

Neutron-induced soft error rate estimation for SRAM using PHITS

Shusuke Yoshimoto, Shintaro Izumi, Masahiko Yoshimoto, 2012, 2012 IEEE 18th International On-Line Testing Symposium (IOLTS).

A 0.38-V operating STT-MRAM with process variation tolerant sense amplifier

Koji Yanagida, Shusuke Yoshimoto, Shintaro Izumi, 2013, 2013 IEEE Asian Solid-State Circuits Conference (A-SSCC).

An 8-bit I/O-sized ADC with second-order TDC and MOM capacitor voltage-to-time converter

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2014, 2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS).

STT-MRAM Operating at 0.38V Using Negative-Resistance Sense Amplifier

Koji Yanagida, Shusuke Yoshimoto, Shintaro Izumi, 2014, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A 50% Power Reduction in H.264/AVC HDTV Video Decoder LSI by Dynamic Voltage Scaling in Elastic Pipeline

Masahiko Yoshimoto, Hiroshi Kawaguchi, Kentaro Kawakami, 2006, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

/spl mu/ITRON-LP: power-conscious real-time OS based on cooperative voltage scaling for multimedia applications

Hiroshi Kawaguchi, Takayasu Sakurai, Youngsoo Shin, 2005, IEEE Transactions on Multimedia.

A 2.23 ps RMS jitter 3 μs fast settling ADPLL using temperature compensation PLL controller

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2014, 2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS).

A 10T Non-Precharge Two-Port SRAM for 74% Power Reduction in Video Processing

Masahiko Yoshimoto, Hidehiro Fujiwara, Koji Nii, 2007, IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07).

A 14 µA ECG processor with robust heart rate monitor for a wearable healthcare system

Hiroshi Nakajima, Shintaro Izumi, Masahiko Yoshimoto, 2013, 2013 Proceedings of the ESSCIRC (ESSCIRC).

Integrated Camera Solution

Hiroshi Kawaguchi, Mikio Sugiyama, Kazuhiko Takami, 2006 .

Low-Power High-Speed Reduced-Clock-Swing Flip-Flops Based on Contention Reduction Techniques

Hiroshi Kawaguchi, Takayasu Sakurai, Muhammad Yazid, 2005 .

0.5-V 4-MB Variation-Aware Cache Architecture Using 7T/14T SRAM and Its Testing Scheme

Shunsuke Okumura, Yohei Nakata, Masahiko Yoshimoto, 2012, IPSJ Trans. Syst. LSI Des. Methodol..

Area Optimization in 6T and 8T SRAM Cells Considering Vth Variation in Future Processes

Masahiko Yoshimoto, Hidehiro Fujiwara, Koji Nii, 2007, IEICE Trans. Electron..

A VGA 30-fps Realtime Optical-Flow Processor Core for Moving Picture Recognition

Masahiko Yoshimoto, Junichi Miyakoshi, Yuichiro Murachi, 2008, IEICE Trans. Electron..

A Sub 100 mW H.264 MP@L4.1 Integer-Pel Motion Estimation Processor Core for MBAFF Encoding with Reconfigurable Ring-Connected Systolic Array and Segmentation-Free, Rectangle-Access Search-Window Buffer

Masahiko Yoshimoto, Masaki Hamamoto, Junichi Miyakoshi, 2008, IEICE Trans. Electron..

Capacitively coupled ECG sensor using a single electrode with adaptive power-line noise cancellation

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2016, 2016 IEEE-EMBS International Conference on Biomedical and Health Informatics (BHI).

Physical activity group classification algorithm using triaxial acceleration and heart rate

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2015, 2015 37th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC).

VTH-hopping scheme to reduce subthreshold leakage for low-power processors

Hiroshi Kawaguchi, Seongsoo Lee, Takayasu Sakurai, 2002, IEEE J. Solid State Circuits.

A low power, VLSI object recognition processor using Sparse FIND feature for 60 fps HDTV resolution video [IEICE Electronics Express Vol. 14(2017) No. 15 pp. 20170668]

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2018, IEICE Electronics Express.

A 168-mW 2.4X-Real-Time 60-kWord Continuous Speech Recognition Processor VLSI

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2013, IEICE Trans. Electron..

FPGA implementation of mixed integer quadratic programming solver for mobile robot control

Masahiko Yoshimoto, Hiroshi Kawaguchi, Hiroki Noguchi, 2009, 2009 International Conference on Field-Programmable Technology.

A single-chip sensor node LSI with synchronous MAC protocol and divided data-buffer SRAM

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2009, 2009 International SoC Design Conference (ISOCC).

Chip-to-Chip Inductive Wireless Power Transmission System for SiP Applications

Hiroshi Kawaguchi, Tadahiro Kuroda, Takayasu Sakurai, 2006, IEEE Custom Integrated Circuits Conference 2006.

Bit-Error and Soft-Error Resilient 7T/14T SRAM with 150-nm FD-SOI Process

Shunsuke Okumura, Shusuke Yoshimoto, Masahiko Yoshimoto, 2012, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

VLSI Architecture of GMM Processing and Viterbi Decoder for 60, 000-Word Real-Time Continuous Speech Recognition

Masahiko Yoshimoto, Hiroshi Kawaguchi, Kazuo Miura, 2011, IEICE Trans. Electron..

Energy-efficient Spin-Transfer Torque RAM cache exploiting additional all-zero-data flags

Yohei Nakata, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2013, International Symposium on Quality Electronic Design (ISQED).

A Wearable Healthcare System With a 13.7 $\mu$ A Noise Tolerant ECG Processor

Hiroshi Nakajima, Shintaro Izumi, Masahiko Yoshimoto, 2015, IEEE Transactions on Biomedical Circuits and Systems.

A 40 nm 144 mW VLSI Processor for Real-Time 60-kWord Continuous Speech Recognition

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2012, IEEE Trans. Circuits Syst. I Regul. Pap..

A reduced clock-swing flip-flop (RCSFF) for 63% power reduction

Hiroshi Kawaguchi, Takayasu Sakurai, H. Kawaguchi, 1998, IEEE J. Solid State Circuits.

Processor Coupling Architecture for Aggressive Voltage Scaling on Multicores

Shunsuke Okumura, Yohei Nakata, Shintaro Izumi, 2012, ARCS Workshops.

A Fast Settling All Digital PLL Using Temperature Compensated Oscillator Tuning Word Estimation Algorithm

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2015, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A Controller LSI for Realizing VDD-Hopping Scheme with Off-the-Shelf Processors and Its Application to MPEG4 System

Hiroshi Kawaguchi, Seongsoo Lee, Takayasu Sakurai, 2002 .

A 19-μA metabolic equivalents monitoring SoC using adaptive sampling

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2017, 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC).

Implementing Virtual Agent as an Interface for Smart Home Voice Control

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2012, 2012 19th Asia-Pacific Software Engineering Conference.

A 51-dB SNDR DCO-based TDC using two-stage second-order noise shaping

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2012, 2012 IEEE International Symposium on Circuits and Systems.

Aggregation Efficiency-Aware Greedy Incremental Tree Routing for Wireless Sensor Networks

Masahiko Yoshimoto, Hiroshi Kawaguchi, Chikara Ohta, 2006, IEICE Trans. Commun..

A 6.14µA normally-off ECG-SoC with noise tolerant heart rate extractor for wearable healthcare systems

Hiroshi Nakajima, Koji Yanagida, Shusuke Yoshimoto, 2014, 2014 IEEE Biomedical Circuits and Systems Conference (BioCAS) Proceedings.

An Architecture Study of Scalable Optical-Flow Processor for Real-Time Video Segmentation

Masahiko Yoshimoto, Junichi Miyakoshi, Hiroshi Kawaguchi, 2004 .

Closed-Form Expressions for Crosstalk Noise and Worst-Case Delay on Capacitively Coupled Distributed RC Lines

Hiroshi Kawaguchi, Takayasu Sakurai, Danardono Dwi Antono, 2007, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A Low-Power Real-Time SIFT Descriptor Generation Engine for Full-HDTV Video Recognition

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2011, IEICE Trans. Electron..

Noise Tolerant Heart Rate Extraction Algorithm Using Short-Term Autocorrelation for Wearable Healthcare Systems

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2015, IEICE Trans. Inf. Syst..

Delay and noise formulas for capacitively coupled distributed RC lines

Hiroshi Kawaguchi, Takayasu Sakurai, H. Kawaguchi, 1998, Proceedings of 1998 Asia and South Pacific Design Automation Conference.

A 40-nm 256-Kb Half-Select Resilient 8T SRAM with Sequential Writing Technique

Shunsuke Okumura, Shusuke Yoshimoto, Masahiko Yoshimoto, 2012, IEICE Electron. Express.

A Low-Latency DMR Architecture with Fast Checkpoint Recovery Scheme

Yohei Nakata, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2015, IEICE Trans. Electron..

A 40-nm Resilient Cache Memory for Dynamic Variation Tolerance Delivering ×91 Failure Rate Improvement under 35% Supply Voltage Fluctuation

Hiroyuki Kawai, Shunsuke Okumura, Yohei Nakata, 2014, IEICE Trans. Electron..

Instantaneous Heart Rate detection using short-time autocorrelation for wearable healthcare systems

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2012, 2012 Annual International Conference of the IEEE Engineering in Medicine and Biology Society.

Virtualization: System-Level Fault Simulation of SRAM Errors in Automotive Electronic Control Systems

Yohei Nakata, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2019 .

A Low-Latency DMR Architecture with Efficient Recovering Scheme Exploiting Simultaneously Copiable SRAM

Yohei Nakata, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2014, ARCS Workshops.

A Process-Variation-Adaptive Network-on-Chip with Variable-Cycle Routers

Masahiko Yoshimoto, Hiroshi Kawaguchi, Yukihiro Takeuchi, 2011, 2011 14th Euromicro Conference on Digital System Design.

An H.264/AVC MP@L4.1 quarter-pel motion estimation processor VLSI for real-time MBAFF encoding

Masahiko Yoshimoto, Masaki Hamamoto, Junichi Miyakoshi, 2008, 2008 15th IEEE International Conference on Electronics, Circuits and Systems.

Divided Static Random Access Memory for Data Aggregation in Wireless Sensor Nodes

Shintaro Izumi, Masahiko Yoshimoto, Hidehiro Fujiwara, 2012, IEICE Trans. Commun..

Professional Development System of Engineers at the Society of Automotive Engineers of Japan

Hiroshi Kawaguchi, Shuji Shiraishi, Takashi Saika, 2012 .

Impact of aggregation efficiency on GIT routing for wireless sensor networks

Masahiko Yoshimoto, Hiroshi Kawaguchi, Chikara Ohta, 2006, 2006 International Conference on Parallel Processing Workshops (ICPPW'06).

A Sub-mW H.264 Baseline-Profile Motion Estimation Processor Core with a VLSI-Oriented Block Partitioning Strategy and SIMD/Systolic-Array Architecture

Masahiko Yoshimoto, Masaki Hamamoto, Junichi Miyakoshi, 2006, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Non-Contact Instantaneous Heart Rate Extraction System Using 24-GHz Microwave Doppler Sensor

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2019, IEICE Trans. Commun..

Swallowable sensing device for long-term gastrointestinal tract monitoring

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2016, 2016 38th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC).

A Low-Power Multi Resolution Spectrum Sensing Architecture for a Wireless Sensor Network with Cognitive Radio

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2011, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A low memory bandwidth Gaussian mixture model (GMM) processor for 20,000-word real-time speech recognition FPGA system

Masahiko Yoshimoto, Hiroshi Kawaguchi, Kazuo Miura, 2008, 2008 International Conference on Field-Programmable Technology.

Integrated control system between active control suspension and four wheel steering for the 1989 CELICA

Hiroshi Kawaguchi, Hiroyuki Ohno, Kaoru Ohashi, 1990 .

A Counter-based Read Circuit Tolerant to Process Variation for 0.4-V Operating STT-MRAM

Koji Yanagida, Shusuke Yoshimoto, Shintaro Izumi, 2016, IPSJ Trans. Syst. LSI Des. Methodol..

Capacitively coupled ECG sensor system with digitally assisted noise cancellation for wearable application

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2017, 2017 IEEE Biomedical Circuits and Systems Conference (BioCAS).

Non-contact and noise tolerant heart rate monitoring using microwave doppler sensor and range imagery

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2015, 2015 37th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC).

Noise tolerant QRS detection using template matching with short-term autocorrelation

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2014, 2014 36th Annual International Conference of the IEEE Engineering in Medicine and Biology Society.

A Process-Variation-Adaptive Network-on-Chip with Variable-Cycle Routers and Variable-Cycle Pipeline Adaptive Routing

Masahiko Yoshimoto, Hiroshi Kawaguchi, Yohei Nakata, 2012, IEICE Trans. Electron..

A 433-MHz Rail-to-Rail Voltage Amplifier with Carrier Sensing Function for Wireless Sensor Networks

Masahiko Yoshimoto, Hiroshi Kawaguchi, Chikara Ohta, 2009, IEICE Trans. Electron..

Proton nuclear magnetic resonance and pattern recognition analysis of liver extracts from rats under different anesthetics

Hiroshi Kawaguchi, Atsuhiro Sakamoto, Tomoyuki Tajima, 2012, BMC Medical Imaging.

A Sub-100 mW Dual-Core HOG Accelerator VLSI for Parallel Feature Extraction Processing for HDTV Resolution Video

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2013, IEICE Trans. Electron..

A 2.4 pJ ferroelectric-based non-volatile flip-flop with 10-year data retention capability

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2014, 2014 IEEE Asian Solid-State Circuits Conference (A-SSCC).

28-nm FD-SOI Dual-Port SRAM with MSB-Based Inversion Logic for Low-Power Deep Learning

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2018, 2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS).

Introducing Multiple Microphone Arrays for Enhancing Smart Home Voice Control (応用音響)

Masahiko Yoshimoto, Hiroshi Kawaguchi, Masahide Nakamura, 2013 .

A low power, VLSI object recognition processor using Sparse FIND feature for 60 fps HDTV resolution video

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2017, IEICE Electron. Express.

A 62-dB SNDR second-order gated ring oscillator TDC with two-stage dynamic D-type flipflops as a quantization noise propagator

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2012, 10th IEEE International NEWCAS Conference.

PAPER Special Section on Analog Circuits and Related SoC Integration Technologies A 433-MHz Rail-to-Rail Voltage Amplifier with Carrier Sensing Function for Wireless Sensor Networks

Masahiko Yoshimoto, Hiroshi Kawaguchi, Takashi Takeuchi, 2009 .

A 14µA ECG processor with noise tolerant heart rate extractor and FeRAM for wearable healthcare systems

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2015, The 20th Asia and South Pacific Design Automation Conference.

A 40 nm 144 mW VLSI Processor for Real-Time 60-kWord Continuous Speech Recognition

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2012, IEEE Transactions on Circuits and Systems I: Regular Papers.

Low-Traffic and Low-Power Data-Intensive Sound Acquisition with Perfect Aggregation Specialized for Microphone Array Networks

Masahiko Yoshimoto, Hiroshi Kawaguchi, Hiroki Noguchi, 2010, 2010 Fourth International Conference on Sensor Technologies and Applications.

Positioning system for mobile terminals using a microphone array network as an intuitive interface

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2011, 2011 Joint Workshop on Hands-free Speech Communication and Microphone Arrays.

Block-basis on-line BIST architecture for embedded SRAM using wordline and bitcell voltage optimal control

Yuki Kagiyama, Shunsuke Okumura, Yohei Nakata, 2011, 2011 12th International Symposium on Quality Electronic Design.

Design Solutions for a Multi-Object Wireless Power Transmission Sheet Based on Plastic Switches

Hiroshi Kawaguchi, Takao Someya, Takayasu Sakurai, 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

Low-Jitter Design for Second-Order Time-to-Digital Converter Using Frequency Shift Oscillators

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2015, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A 40-nm 168-mW 2.4×-real-time VLSI processor for 60-kWord continuous speech recognition

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2012, Proceedings of the IEEE 2012 Custom Integrated Circuits Conference.

12.5-m Distance Measurement in High-Interference Environment Using Ultrasonic Array Sensors

Shintaro Izumi, Hiroshi Kawaguchi, Yukiko Yoshikawa, 2021, 2021 IEEE International Instrumentation and Measurement Technology Conference (I2MTC).

High mobility of pentacene field-effect transistors with polyimide gate dielectric layers

Hiroshi Kawaguchi, Takao Someya, Takayasu Sakurai, 2004 .

Development of the High-Power, Low-Emission Engine for the “Honda S2000”

Hiroshi Kawaguchi, Yutaka Otobe, H. Kawaguchi, 2000 .

Control of threshold voltage of organic field-effect transistors with double-gate structures

Hiroshi Kawaguchi, Takao Someya, Takayasu Sakurai, 2005 .

Half VDD Clock-Swing Flip-Flop with Reduced Contention for up to 60% Power Saving in Clock Distribution

Hiroshi Kawaguchi, Takayasu Sakurai, Makoto Takamiya, 2007, ESSCIRC 2007 - 33rd European Solid-State Circuits Conference.

Organic field-effect transistors with bending radius down to 1 mm

Hiroshi Kawaguchi, Takao Someya, Takayasu Sakurai, 2004 .

8-3 Managing Leakage in Charge-Based Analog Circuits with Low-VTH Transistors by Analog T-Switch ( AT-Switch ) and Super Cut-off CMOS

Hiroshi Kawaguchi, Kouichi Kanda, Takayasu Sakurai, 2005 .

6.3 A 0.5V, 400MHz, VDD-Hopping Processor with Zero-VTH FD-SOI Technology

Hiroshi Kawaguchi, Kouichi Kanda, Takayasu Sakurai, 2003 .

Optimum Device Parameters and Scalability of Variable Threshold Voltage Complementary MOS (VTCMOS)

Hiroshi Kawaguchi, Takayasu Sakurai, Makoto Takamiya, 2001 .

6-3 Vth-Hopping Scheme for 82% Power Saving in Low-Voltage Processors

Hiroshi Kawaguchi, Takayasu Sakurai, Koichi Nose, 2000 .

Experimental Evaluation of Cooperative Voltage Scaling ( CVS ) : A Case Study

Hiroshi Kawaguchi, Takayasu Sakurai, Youngsoo Shin, 2001 .