W. Huott

A 5.6GHz 64kB Dual-Read Data Cache for the POWER6TM Processor

D. Plass, J. Davis, P. Bunce, 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

6.6+ GHz Low Vmin, read and half select disturb-free 1.2 Mb SRAM

W. Huott, R. Houle, R. Joshi, 2007, 2007 IEEE Symposium on VLSI Circuits.

Non-invasive timing analysis of IBM G6 microprocessor L1 cache using backside time-resolved hot electron luminescence

W. Huott, S. Polonsky, D. Knebel, 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

609 MHz G5 S/399 microprocessor

Y.H. Chan, E. Schwarz, W. Huott, 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).

A Low Power and High Performance SOI SRAM Circuit Design with Improved Cell Stability

R.V. Joshi, R. Freese, P. Patel, 2006, 2006 IEEE international SOI Conferencee Proceedings.

A high performance 2.4 Mb L1 and L2 cache compatible 45nm SRAM with yield improvement capabilities

R. Kanj, W. Huott, R. Houle, 2008, 2008 IEEE Symposium on VLSI Circuits.

IBM zEnterpriseTM energy efficient 5.2Ghz processor chip

S. Carey, B. Curran, D. Plass, 2011, 2011 IEEE International Conference on IC Design & Technology.