B. Woolery

Reliability studies of a 22nm SoC platform technology featuring 3-D tri-gate, optimized for ultra low power, high performance and high density application

A. Rahman, C. Tsai, P. Bai, 2013, 2013 IEEE International Reliability Physics Symposium (IRPS).

Erratic fluctuations of sram cache vmin at the 90nm process technology node

J. Jopling, M. Jones, M. Agostinelli, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

Gate dielectric TDDB characterizations of advanced High-k and metal-gate CMOS logic transistor technology

C. Prasad, S. Ramey, J. Hicks, 2012, 2012 IEEE International Reliability Physics Symposium (IRPS).