Ashutosh Nandi

发表

Design of Bandgap Voltage Reference Circuit using LV and LP Current Conveyor

Shishu Pal, Ashutosh Nandi, 2018, 2018 4th International Conference on Computing Communication and Automation (ICCCA).

Design of IIR Filter Using Wallace Tree Multiplier

Ashutosh Nandi, Karishma Malviya, 2018, 2018 2nd International Conference on Power, Energy and Environment: Towards Smart Technology (ICEPE).

Comparative study of 16-order FIR filter design using different multiplication techniques

Disha Yadav, Ashutosh Nandi, Anubhuti Mittal, 2017, IET Circuits Devices Syst..

Fringe capacitance model of a double-gate MOSFET with gate underlap

Ashutosh Nandi, Pruthvi Raj Kosala, Ashutosh Nandi, 2016, 2016 IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT).

Design and Analysis of Sub-DT Sub-Domino Logic Circuits for Ultra Low Power Applications

Rajeevan Chandel, Ashutosh Nandi, 2010, J. Low Power Electron..

Oxide thickness and S/D junction depth based variation aware OTA design using underlap FinFET

Sudeb Dasgupta, Ashok K. Saxena, Ashutosh Nandi, 2016, Microelectron. J..

Analog Performance Analysis of Dual-k Spacer Based Underlap FinFET

Sudeb Dasgupta, Ashok K. Saxena, Ashutosh Nandi, 2012, VDAT.

Design of FIR Filter Using FCSD Representation

Neha Goel, Ashutosh Nandi, 2015, 2015 IEEE International Conference on Computational Intelligence & Communication Technology.

Design of four point Radix-2 FFT structure on Xilinx

Avinash Kumar Singh, Ashutosh Nandi, 2017, 2017 International Conference on Intelligent Computing and Control (I2C2).

Modified Error Tolerant Adder for Digital Signal Processing Applictaion

Hardik Patel, Ashutosh Nandi, Ashutosh Nandi, 2016, 2016 International Conference on Micro-Electronics and Telecommunication Engineering (ICMETE).

Design and Analysis of Analog Performance of Dual-k Spacer Underlap N/P-FinFET at 12 nm Gate Length

Sudeb Dasgupta, Ashok K. Saxena, Ashutosh Nandi, 2013, IEEE Transactions on Electron Devices.

Effect of air spacer in underlap GAA nanowire: an analogue/RF perspective

Shikhar Gupta, Ashutosh Nandi, Ashutosh Nandi, 2019, IET Circuits Devices Syst..

Enhancing the SRAM performance of gate-stacked DG-MOSFET

Ashutosh Nandi, Mitashra Gupta, 2017, 2017 2nd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT).

Comparative analysis of digital IIR filter using add and shift method on Xilinx platform

Disha Yadav, Ashutosh Nandi, 2016, 2016 International Conference on Control, Instrumentation, Communication and Computational Technologies (ICCICCT).

Process Corner Analysis of 2-stage Op-Amp Using Low Supply Voltage Current Mirror

Ashutosh Nandi, Pallabee Biswas, 2018, 2018 Second International Conference on Intelligent Computing and Control Systems (ICICCS).

Temperature analysis of underlap GAA-SNWTs for analog/RF applications

Shikhar Gupta, Ashutosh Nandi, Ashutosh Nandi, 2019, Microelectron. J..

Robust Subthreshold Circuit Designing Using Sub-threshold Source Coupled Logic (STSCL)

Amit Kumar Jaiswal, Gaurav Saini, Kamal Kant, 2010 .

Impact of dual-k spacer on analog performance of underlap FinFET

Sudeb Dasgupta, Ashok K. Saxena, Ashutosh Nandi, 2012, Microelectron. J..

Analytical Modeling of a Double Gate MOSFET Considering Source/Drain Lateral Gaussian Doping Profile

Sudeb Dasgupta, Ashok K. Saxena, Ashutosh Nandi, 2013, IEEE Transactions on Electron Devices.

Performance analysis of junctionless DG‐MOSFET‐based 6T‐SRAM with gate‐stack configuration

Ashutosh Nandi, Shubham Tayal, 2018, Micro & Nano Letters.

Enhancing Low Temperature Analog Performance of Underlap FinFET at Scaled Gate Lengths

Sudeb Dasgupta, Ashok K. Saxena, Ashutosh Nandi, 2014, IEEE Transactions on Electron Devices.