Thomas Eudes

Cancellation of Delays in the High-Rate Interconnects with UWB NGD Active Cells

Blaise Ravelo, Thomas Eudes, B. Ravelo, 2011 .

Modelling of the Signal Delay Induced by PCB Interconnect SISO Structure

Blaise Ravelo, Thomas Eudes, 2020 .

Fast estimation of high-speed signal integrity for coupled PCB interconnects

Thierry Lacrevaz, Bernard Flechet, Blaise Ravelo, 2013, 2013 17th IEEE Workshop on Signal and Power Integrity.

Electrical performance modeling of unbalanced comb tree networks on advanced PCB interconnects for high-rate clock signal distribution

Thierry Lacrevaz, Bernard Flechet, Blaise Ravelo, 2013, 2013 IEEE 63rd Electronic Components and Technology Conference.

Analysis of multi-gigabits signal integrity through clock H-tree

Blaise Ravelo, Thomas Eudes, 2013, Int. J. Circuit Theory Appl..

Basic Analysis of Single-Input Single-Output (SISO) PCB Interconnect Structure

Blaise Ravelo, Thomas Eudes, 2020 .

Fast estimation of RL-loaded microelectronic interconnections delay for the signal integrity prediction

Blaise Ravelo, Thomas Eudes, 2012 .

TRANSIENT RESPONSE CHARACTERIZATION OF THE HIGH-SPEED INTERCONNECTION RLCG-MODEL FOR THE SIGNAL INTEGRITY ANALYSIS

Blaise Ravelo, Anne Louis, Thomas Eudes, 2011 .