Jing-Jia Liou

发表

BIST-based diagnosis scheme for field programmable gate array interconnect delay faults

Cheng-Wen Wu, Chih-Tsun Huang, Yen-Lin Peng, 2007, IET Comput. Digit. Tech..

A Region-Based Framework for Design Feature Identification of Systematic Process Variations

Jing-Jia Liou, Shuo-You Hsu, Chih-Hsiang Hsu, 2013, 2013 22nd Asian Test Symposium.

Delay defect coverage for FPGA test configurations based on statistical evaluation

Cheng-Wen Wu, Chih-Tsun Huang, Yen-Lin Peng, 2005, 2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT)..

An Energy and Timing Model for NoC with DVFS Links and its Application of Energy Optimization

Jing-Jia Liou, 余宗盛, Tsung-Sheng Yu, 2011 .

Handling Pattern-Dependent Delay Faults in Diagnosis

Ying-Yen Chen, Jing-Jia Liou, Jyun-Wei Chen, 2007, 25th IEEE VLSI Test Symposium (VTS'07).

Cost reduction of system-level tests with stressed structural tests and SVM

Jing-Jia Liou, Meng-Ta Hsieh, Jun-Fei Cherng, 2015, 2015 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC).

Fast statistical timing analysis by probabilistic event propagation

Kwang-Ting Cheng, Sandip Kundu, Angela Krstic, 2001, DAC '01.

Enhancing test efficiency for delay fault testing using multiple-clocked schemes

M. Ray Mercer, Rohit Kapur, Thomas W. Williams, 2002, DAC '02.

Delay Defect Diagnosis Based Upon Statistical Timing Models - The First Step

Kwang-Ting Cheng, Magdy S. Abadir, Angela Krstic, 2003, DATE.

An application-independent delay testing methodology for island-style FPGA

Cheng-Wen Wu, Chih-Tsun Huang, Yen-Lin Peng, 2004 .

Delay defect diagnosis based upon statistical timing models - the first step [logic testing]

Kwang-Ting Cheng, Magdy S. Abadir, Angela Krstic, 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

iScan: Indirect-access scan test over HOY test platform

Shi-Yu Huang, Hsi-Pin Ma, Cheng-Wen Wu, 2009, 2009 International Symposium on VLSI Design, Automation and Test.

Multiple-Core under Test Architecture for HOY Wireless Testing Platform

Ying-Yen Chen, Jing-Jia Liou, Chun-Yu Yang, 2009, 2009 Asian Test Symposium.

Area and Test Cost Reduction for On-Chip Wireless Test Channels with System-Level Design Techniques

Cheng-Wen Wu, Chih-Tsun Huang, Chun-Kai Hsu, 2008, 2008 17th Asian Test Symposium.

Enhancing Diagnosis Resolution For Delay Faults By Path Extension Method

Ying-Yen Chen, Jing-Jia Liou, 2006, 2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

Timing yield estimation with clock network correlations by propagating discrete probability distributions

Jing-Jia Liou, Youngsoo Shin, Lee-eun Yu, 2009, 2009 IEEE International Conference on IC Design and Technology.

Diagnosis Framework for Locating Failed Segments of Path Delay Faults

Ying-Yen Chen, Jing-Jia Liou, 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

TurboVG: A HW/SW co-designed multi-core OpenVG accelerator for vector graphics applications with embedded power profiler

Yeh-Ching Chung, Chih-Tsun Huang, Jing-Jia Liou, 2011, 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011).

Critical path selection for delay fault testing based upon a statistical timing model

Kwang-Ting Cheng, Li-C. Wang, Jing-Jia Liou, 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Automatic Test Wrapper Synthesis for a Wireless ATE Platform

Ying-Yen Chen, Jing-Jia Liou, Chun-Yu Yang, 2010, IEEE Design & Test of Computers.

Multiple-Core Testing Architecture for HOY Wireless Testing Platform

Jing-Jia Liou, Sung-Yu Chen, 陳松裕, 2009 .

High Quality Pattern Generation for Delay Defects with Functional Sensitized Paths

Jing-Jia Liou, Augusli Kifli, Ming-Ting Hsieh, 2008, 2008 17th Asian Test Symposium.

A FPGA Implementation of Farneback Optical Flow by High-Level Synthesis

Chia-Wei Chang, Jing-Jia Liou, Zi-Qi Zhong, 2019, FPGA.

Modeling, testing, and analysis for delay defects and noise effects in deep submicron devices

Kwang-Ting Cheng, Angela Krstic, Jing-Jia Liou, 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Delay testing considering crosstalk-induced effects

Kwang-Ting Cheng, Angela Krstic, Jing-Jia Liou, 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

A low-cost wireless interface with no external antenna and crystal oscillator for Cm-range contactless testing

Shi-Yu Huang, Hsi-Pin Ma, Cheng-Wen Wu, 2011, 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC).

On structural vs. functional testing for delay faults

Kwang-Ting Cheng, Angela Krstic, Li-C. Wang, 2003, Fourth International Symposium on Quality Electronic Design, 2003. Proceedings..

Pseudo-Multiple-Exposure-Based Tone Fusion With Local Region Adjustment

Ching-Te Chiu, Jing-Jia Liou, Chun-Yi Lin, 2015, IEEE Transactions on Multimedia.

Experience in critical path selection for deep sub-micron delay test and timing validation

Kwang-Ting Cheng, Angela Krstic, Li-C. Wang, 2003, ASP-DAC '03.

On error modeling of electrical bugs for post-silicon timing validation

Kwang-Ting Cheng, Jing-Jia Liou, Ming Gao, 2012, 17th Asia and South Pacific Design Automation Conference.

Diagnosis of delay defects using statistical timing models

Kwang-Ting Cheng, Angela Krstic, Li-C. Wang, 2003, Proceedings. 21st VLSI Test Symposium, 2003..

False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation

Kwang-Ting Cheng, Angela Krstic, Li-C. Wang, 2002, DAC '02.

On theoretical and practical considerations of path selection for delay fault testing

Kwang-Ting Cheng, Li-C. Wang, Jing-Jia Liou, 2002, ICCAD 2002.

Optimization for application-specific packet-based on-chip interconnects using a cycle-accurate model

Chih-Tsun Huang, Jing-Jia Liou, Chi-Feng Wu, 2017, 2017 International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

AF-Test: Adaptive-Frequency Scan Test Methodology for Small-Delay Defects

Shi-Yu Huang, Hsi-Pin Ma, Cheng-Wen Wu, 2010, 2010 IEEE 25th International Symposium on Defect and Fault Tolerance in VLSI Systems.

Analysis of delay test effectiveness with a multiple-clock scheme

M. Ray Mercer, Rohit Kapur, Thomas W. Williams, 2002, Proceedings. International Test Conference.

Design of high-throughput Inter-PE communication with application-level flow control protocol for many-core architectures

Chih-Tsun Huang, Jing-Jia Liou, Ting-Shuo Hsu, 2013, MES '13.

AC-Plus Scan Methodology for Small Delay Testing and Characterization

Shi-Yu Huang, Hsi-Pin Ma, Cheng-Wen Wu, 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Diagnosis of Failed Segments for Path Delay Faults

Jing-Jia Liou, Min-Pin Kuo, 2004 .

Performance sensitivity analysis using statistical method and its applications to delay

Kwang-Ting Cheng, Sandip Kundu, Angela Krstic, 2000, ASP-DAC '00.

Diagnosis framework for locating failed segments of path delay faults

Ying-Yen Chen, Jing-Jia Liou, Min-Pin Kuo, 2005, IEEE International Conference on Test, 2005..

Performance sensitivity analysis using statistical methods and its applications to delay testing

Kwang-Ting Cheng, Sandip Kundu, Jing-Jia Liou, 2000, Proceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106).

Exploring linear structures of critical path delay faults to reduce test efforts

Pei-Ying Hsieh, Jing-Jia Liou, Shun-Yen Lu, 2006, ICCAD.

Test Cost Reduction for Performance Yield Recovery by Classification of Multiple-Clock Test Data

Jing-Jia Liou, Ting-Shuo Hsu, Jun-Hua Kuo, 2012, 2012 IEEE 21st Asian Test Symposium.

Sampling Correlation Sources for Timing Yield Analysis of Sequential Circuits with Clock Networks

Jing-Jia Liou, Youngsoo Shin, Seungwhun Paik, 2011, J. Circuits Syst. Comput..

Enhancing diagnosis resolution for delay defects based upon statistical timing and statistical fault models

Kwang-Ting Cheng, Angela Krstic, Li-C. Wang, 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

An application-independent delay testing methodology for island-style FPGA

Cheng-Wen Wu, Chih-Tsun Huang, Yen-Lin Peng, 2004, 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2004. DFT 2004. Proceedings..

An efficient SAT-based path delay fault ATPG with an unified sensitization model

Jing-Jia Liou, Ming-Ting Hsieh, Shun-Yen Lu, 2007, 2007 IEEE International Test Conference.

Path selection and pattern generation for dynamic timing analysis considering power supply noise effects

Kwang-Ting Cheng, Angela Krstic, Jing-Jia Liou, 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

An ISA-level Accurate Fault Simulator for System-level Fault Analysis

Jing-Jia Liou, Ting-Shuo Hsu, Christian M. Fuchs, 2020, 2020 IEEE 29th Asian Test Symposium (ATS).

NNSim: A Fast and Accurate SystemC/TLM Simulator for Deep Convolutional Neural Network Accelerators

Jing-Jia Liou, Ting-Shuo Hsu, Juin-Ming Lu, 2019, 2019 International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

Design space exploration with a cycle-accurate systemC/TLM DRAM controller model

Chih-Tsun Huang, Jing-Jia Liou, Ting-Shuo Hsu, 2017, 2017 International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

Statistical Timing Analysis By Propagation

Kwang-Ting Cheng, Angela Krstic, Jing-Jia Liou, 2001 .

Diagnosis-assisted supply voltage configuration to increase performance yield of cell-based designs

Ying-Yen Chen, Chun-Chia Chen, Jing-Jia Liou, 2011, 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011).

Wireless Testing of RAM Chips by HOY: Methodology, Architecture, and Prototype Implementation

Hsi-Pin Ma, Cheng-Wen Wu, Jing-Jia Liou, 2008 .

Post-Silicon Test Flow for Aging Prediction

Jing-Jia Liou, Ting-Shuo Hsu, Zih-Huan Gao, 2017, 2017 IEEE 26th Asian Test Symposium (ATS).

On theoretical and practical considerations of path selection for delay fault testing

Kwang-Ting Cheng, Li-C. Wang, Jing-Jia Liou, 2002, IEEE/ACM International Conference on Computer Aided Design, 2002. ICCAD 2002..

A fast and accurate network-on-chip timing simulator with a flit propagation model

Jing-Jia Liou, Ting-Shuo Hsu, Chao-Kai Yu, 2015, The 20th Asia and South Pacific Design Automation Conference.

Automatic Wrapper Synthesis and Test Program Generation for Packet-based ATE Platforms

Jing-Jia Liou, Y.-Y. Chen, C.-U. Yang, 2008 .

Memory-aware power modeling for PAC DSP core

Shi-Yu Huang, Jen-Chieh Yeh, Jing-Jia Liou, 2009, 2009 1st Asia Symposium on Quality Electronic Design.

A BIST scheme for FPGA interconnect delay faults

Cheng-Wen Wu, Chun-Chieh Wang, Chih-Tsun Huang, 2005, 23rd IEEE VLSI Test Symposium (VTS'05).

Design and analysis of a many-core processor architecture for multimedia applications

Chih-Tsun Huang, Jing-Jia Liou, Ting-Shuo Hsu, 2012, Proceedings of The 2012 Asia Pacific Signal and Information Processing Association Annual Summit and Conference.

Design of a scalable many-core processor for embedded applications

Chih-Tsun Huang, Jing-Jia Liou, Ting-Shuo Hsu, 2015, The 20th Asia and South Pacific Design Automation Conference.

A prototype of a wireless-based test system

Ying-Yen Chen, Hsi-Pin Ma, Cheng-Wen Wu, 2007, SoCC.

Methodology of exploring ESL/RTL many-core platforms for developing embedded parallel applications

Chih-Tsun Huang, Liang-Chia Cheng, Jing-Jia Liou, 2014, 2014 27th IEEE International System-on-Chip Conference (SOCC).

Chip clustering with mutual information on multiple clock tests and its application to yield tuning

Jing-Jia Liou, Ting-Shuo Hsu, Jun-Hua Kuo, 2014, 2014 IEEE 32nd International Conference on Computer Design (ICCD).

Extraction of Statistical Timing Profiles Using Test Data

Ying-Yen Chen, Jing-Jia Liou, 2007, 2007 44th ACM/IEEE Design Automation Conference.

Analyzing Transient Faults and Functional Error Rates of a RISC-V Core: A Case Study

Jing-Jia Liou, Dun-An Yang, Harry H. Chen, 2021, 2021 IEEE 30th Asian Test Symposium (ATS).

Tile-Based Architecture Exploration for Convolutional Accelerators in Deep Neural Networks

Chih-Tsun Huang, Jing-Jia Liou, Juin-Ming Lu, 2021, 2021 IEEE 3rd International Conference on Artificial Intelligence Circuits and Systems (AICAS).

False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation

Jing-Jia Liou, Kwang-Ting Cheng, A. Krstic, 2002, Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324).

Fast statistical timing analysis by probabilistic event propagation

Kwang-Ting Cheng, Jing-Jia Liou, S. Kundu, 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

Exploring Linear Structures of Critical Path Delay Faults to Reduce Test Efforts

Jing-Jia Liou, Shun-Yen Lu, Pei-Ying Hsieh, 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.