Sunil R. Das

发表

An adaptive path selection method for delay testing

Wen-Ben Jone, Wu-Sung Yeh, Chingwei Yeh, 2001, IEEE Trans. Instrum. Meas..

Designing Home Security and Monitoring System Based on Field Programmable Gate Array*

Sunil R. Das, Voicu Groza, Mansour H. Assaf, 2014 .

On the design of improved failure detection experiments in synchronous sequential machines based on terminal measurements

Sunil R. Das, Zen Chen, S. M. Wu, 1979 .

Fault tolerance in systems design in VLSI using data compression under constraints of failure probabilities

Wen-Ben Jone, Sunil R. Das, C. V. Ramamoorthy, 2001, IEEE Trans. Instrum. Meas..

Instrumentation applications of multibit random-data representation

Sunil R. Das, Voicu Groza, Emil M. Petriu, 2003, IEEE Trans. Instrum. Meas..

Image processing based system for classification of vehicles for parking purposes

Sunil R. Das, Voicu Groza, Amit Kumar, 2015, 2015 IEEE International Instrumentation and Measurement Technology Conference (I2MTC) Proceedings.

Guest Editorial Second Special Section of the IEEE Transactions on Instrumentation and Measurement in the Area of VLSI Testing - Future of Semiconductor Test

Sunil R. Das, Rochit Rajsuman, 2006, IEEE Trans. Instrum. Meas..

Fault simulation and response compaction in full scan circuits using HOPE

Wen-Ben Jone, Sunil R. Das, C. V. Ramamoorthy, 2005, IEEE Transactions on Instrumentation and Measurement.

An efficient parallel transparent BIST method for multiple embedded memory buffers

Wen-Ben Jone, Sunil R. Das, Der-Cheng Huang, 2001, VLSI Design 2001. Fourteenth International Conference on VLSI Design.

Probabilistic modeling and fault analysis in sequential logic using computer simulation

Wen-Ben Jone, Sunil R. Das, K. L. Wong, 1990, IEEE Trans. Syst. Man Cybern..

IP core logic fault test simulation environment

Sunil R. Das, Mansour H. Assaf, Emil M. Petriu, 2010, 2010 IEEE Instrumentation & Measurement Technology Conference Proceedings.

Delay Fault Coverage Enhancement Using Variable Observation Times

Wen-Ben Jone, Sunil R. Das, Yun-Pan Ho, 1997, J. Electron. Test..

Space compression revisited

Sunil R. Das, Krishnendu Chakrabarty, Mansour H. Assaf, 2000, IEEE Trans. Instrum. Meas..

An efficient BIST method for non-traditional faults of embedded memory arrays

Wen-Ben Jone, Sunil R. Das, Der-Chen Huang, 2002, IMTC/2002. Proceedings of the 19th IEEE Instrumentation and Measurement Technology Conference (IEEE Cat. No.00CH37276).

Designing zero-aliasing space compressors: graph theory approach

Sunil R. Das, Amiya Nayak, Emil M. Petriu, 2007 .

Guest Editorial First Special Section of the IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT in the Area of VLSI Testing - Future of Semiconductor Test

Sunil R. Das, Rochit Rajsuman, 2005, IEEE Trans. Instrum. Meas..

Circuit Architecture Test Verification Based on Hardware Software Co-design with ModelSim

Sunil R. Das, Mansour H. Assaf, Satyendra N. Biswas, 2013 .

Syndrome Signature in Output Compaction for VLSI Built-in Self-Test

Wen-Ben Jone, Sunil R. Das, Amiya Nayak, 1998, VLSI Design.

Implementation of Embedded Cores-Based Digital Devices in JBits Java Simulation Environment

Sunil R. Das, Voicu Groza, Mansour H. Assaf, 2004, CIT.

Data compression using mixed cascade of nonlinear logic

Sunil R. Das, Voicu Groza, Mansour H. Assaf, 2013, 2013 IEEE International Instrumentation and Measurement Technology Conference (I2MTC).

Designing elementary-tree space compressors using AND/NAND and XOR/XNOR combinations

Sunil R. Das, Voicu Groza, Mansour H. Assaf, 2015, 2015 IEEE International Instrumentation and Measurement Technology Conference (I2MTC) Proceedings.

A stochastic method for defect level analysis of pseudorandom testing

Wen-Ben Jone, Sunil R. Das, 1998, Proceedings Eleventh International Conference on VLSI Design.

DEGRADATION TO REDUCE MISR SIZE IN RIST APPLICATIONS BY NONEXHAUST I VE TEST PATTERNS

Wen-Ben Jone, Sunil R. Das, Amiya Nayak, 1997 .

Enhancing testability in architectural design for the new generation of core-based embedded systems

Sunil R. Das, Mansour H. Assaf, Emil M. Petriu, 2004, Eighth IEEE International Symposium on High Assurance Systems Engineering, 2004. Proceedings..

Multiple-output parity bit signature for exhaustive testing

Wen-Ben Jone, Sunil R. Das, 1990, J. Electron. Test..

On System-on-Chip Testing Using Hybrid Test Vector Compression

Sunil R. Das, Emil M. Petriu, Satyendra Biswas, 2014, IEEE Transactions on Instrumentation and Measurement.

A survey on bit dimension optimization strategies of microprograms

Sunil R. Das, Amiya Nayak, 1990, MICRO.

On random testing of sequential digital logic with a high confidence measure (abstract)

Sunil R. Das, 1986, CSC '86.

Transition submatrices in regular homing experiments and identification of sequential machines of known class using direct-sum transition matrices

Sunil R. Das, Zen Chen, Ping Chao, 1987, Comput. Oper. Res..

Altera Max Plus II Development Environment in Fault Simulation and Test Implementation of Embedded Cores-Based Sequential Circuits

Sunil R. Das, Mansour H. Assaf, Emil M. Petriu, 2004, IWDC.

Measuring availability indexes with small samples for component and network reliability using the Sahinoglu-Libby probability model

Sunil R. Das, Mehmet Sahinoglu, David L. Libby, 2005, IEEE Transactions on Instrumentation and Measurement.

Realizing ultimate compression with acceptable fault coverage degradation to reduce MISR size in BIST applications by nonexhaustive test patterns

Wen-Ben Jone, Sunil R. Das, Amiya Nayak, 1997, Proceedings of 1997 IEEE International Symposium on Circuits and Systems. Circuits and Systems in the Information Age ISCAS '97.

Delay fault coverage enhancement using multiple test observation times

Wen-Ben Jone, Sunil R. Das, Yun-Pan Ho, 1997, Proceedings Tenth International Conference on VLSI Design.

A low power dynamic logic with nMOS based resistive keeper circuit

Sunil R. Das, Mahbubul Haque, Emil M. Petriu, 2017, 2017 International Conference on Innovative Mechanisms for Industry Applications (ICIMIA).

A survey on bit dimension optimization strategies of microprograms

Sunil R. Das, Amiya Nayak, A. Nayak, 1990, [1990] Proceedings of the 23rd Annual Workshop and Symposium@m_MICRO 23: Microprogramming and Microarchitecture.

On probabilistic testing of large-scale sequential circuits using circuit decomposition

Wen-Ben Jone, Sunil R. Das, Amiya Nayak, 1994, Proceedings of 7th International Conference on VLSI Design.

A built-in self-testing method for embedded multiport memory arrays

Wen-Ben Jone, Sunil R. Das, Swaroop Ghosh, 2004, IEEE Transactions on Instrumentation and Measurement.

Instrumentation applications of random-data representation

Emil M. Petriu, Sunil R. Das, L. Zhao, 2000, Proceedings of the 17th IEEE Instrumentation and Measurement Technology Conference [Cat. No. 00CH37066].

Aliasing-free compaction revisited

Sunil R. Das, Emil M. Petriu, Altaf Hossain, 2008, IET Circuits Devices Syst..

Designing general-purpose fault-tolerant distributed systems-a layered approach

Wen-Ben Jone, Sunil R. Das, Amiya Nayak, 1994, Proceedings of 1994 International Conference on Parallel and Distributed Systems.

Test environment for embedded cores-based system-on-chip (soc): development and methodologies

Sunil R. Das, Mansour H. Assaf, Emil M. Petriu, 2006 .

On automated test system for asymmetric digital subscriber line equipment

Sunil R. Das, Mansour H. Assaf, Emil M. Petriu, 2013 .

A parallel built-in self-diagnostic method for embedded memory buffers

Wen-Ben Jone, Sunil R. Das, Der-Cheng Huang, 2001, VLSI Design 2001. Fourteenth International Conference on VLSI Design.

Implementing built-in self-test environment for cores-based digital circuits with Verilog HDL

Sunil R. Das, Mansour H. Assaf, Emil M. Petriu, 2012 .

Low-level logic fault testing ASIC simulation environment

Sunil R. Das, Mansour H. Assaf, Satyendra N. Biswas, 2014 .

Robotic tactile recognition of pseudorandom encoded objects

Sunil R. Das, Ana-Maria Cretu, Emil M. Petriu, 2004, IEEE Transactions on Instrumentation and Measurement.

A compact multispectral image capture unit for deployment on drones

Sunil R. Das, Voicu Groza, Mansour H. Assaf, 2016, 2016 IEEE International Instrumentation and Measurement Technology Conference Proceedings.

On using twisted-ring counters for testing embedded cores in system-on-a-chip designs

Sunil R. Das, Krishnendu Chakrabarty, Anshuman Chandra, 2001, IMTC 2001. Proceedings of the 18th IEEE Instrumentation and Measurement Technology Conference. Rediscovering Measurement in the Age of Informatics (Cat. No.01CH 37188).

Hybrid test vector compression in system-on-chip test — An overview and methodology

Sunil R. Das, Emil M. Petriu, Satyendra N. Biswas, 2009, 2009 4th International Conference on Computers and Devices for Communication (CODEC).

CACOP - A Random Pattern Testability Analyzer

Wen-Ben Jone, Sunil R. Das, 1993, The Sixth International Conference on VLSI Design.

Design and implementation of high-performance master/slave memory controller with microcontroller bus architecture

Sunil R. Das, Voicu Groza, Mansour H. Assaf, 2014, 2014 IEEE International Instrumentation and Measurement Technology Conference (I2MTC) Proceedings.

Face Identification Based on Discrete Wavelet Transform and Neural Networks

Sunil R. Das, Mansour H. Assaf, Satyendra N. Biswas, 2019 .

Logic fault test simulation environment for IP core-based digital systems

Sunil R. Das, Mansour H. Assaf, Emil M. Petriu, 2009, 2009 52nd IEEE International Midwest Symposium on Circuits and Systems.

Use of Session Initiation Protocol in Multimedia Communications: Evaluation of Server Performance Based on Software Profiling

Sunil R. Das, Mansour H. Assaf, Satyendra N. Biswas, 2013 .

ModelSim verification tool in testing cores-based system-on-chips

Sunil R. Das, Amiya Nayak, Emil M. Petriu, 2008 .

Space compactor design in VLSI circuits based on graph theoretic concepts

Sunil R. Das, Emil M. Petriu, Satyendra Biswas, 2005, IEEE Transactions on Instrumentation and Measurement.

Pseudorandom encoding for structured light applications

Sunil R. Das, Emil M. Petriu, Niculaie Trif, 1998, Computers and Their Applications.

A parallel built-in self-diagnostic method for non-traditional faults of embedded memory arrays

Wen-Ben Jone, Sunil R. Das, V. Arora, 2003, Proceedings of the 20th IEEE Instrumentation Technology Conference (Cat. No.03CH37412).

Clause-Column Table Approach for Generating All the Prime Implicants of Switching Functions

Sunil R. Das, N. S. Khabra, Sunil R. Das, 1972, IEEE Transactions on Computers.

Intellectual Property (IP) Cores and a Logic Fault Test Simulation Environment

Sunil R. Das, Mansour H. Assaf, Emil M. Petriu, 2010 .

Cascade of two-input nonlinear logic in designing space compression networks in VLSI

Sunil R. Das, Mansour H. Assaf, Voicu Groza, 2011, 2011 IEEE International Instrumentation and Measurement Technology Conference.

On a New Graph Theory Approach to Designing Zero-Aliasing Space Compressors for Built-In Self-Testing

Wen-Ben Jone, Sunil R. Das, Mansour H. Assaf, 2006, IEEE Transactions on Instrumentation and Measurement.

Syndrome signature in output compaction for VLSI BIST

Wen-Ben Jone, Sunil R. Das, Amiya Nayak, 1996, Proceedings of 9th International Conference on VLSI Design.

Multiform Partial Symmetry and Linearity

Sunil R. Das, N. S. Khabra, 1973, IEEE Transactions on Computers.

Test Response Compaction in VLSI BIST with Array of Two-Input Linear Logic

Sunil R. Das, Alexander R. Applegate, 2011 .

Adaptive scheduled experimentation and fault location in large combinational logic networks

Sunil R. Das, 1988 .

Short duration voice data speaker recognition system using novel fuzzy vector quantization algorithm

Sunil R. Das, Voicu Groza, Mansour H. Assaf, 2016, 2016 IEEE International Instrumentation and Measurement Technology Conference Proceedings.

Energy efficient optimization of wireless embedded sensor networks

Sunil R. Das, Mansour H. Assaf, Satyendra N. Biswas, 2013 .

Revisiting response compaction in space for full-scan circuits with nonexhaustive test sets using concept of sequence characterization

Wen-Ben Jone, Sunil R. Das, C. V. Ramamoorthy, 2005, IEEE Transactions on Instrumentation and Measurement.

Compressed video watermarking technique

Sunil R. Das, Voicu Groza, Mansour H. Assaf, 2013, 2013 IEEE International Instrumentation and Measurement Technology Conference (I2MTC).

Crosstalk test pattern generation for dynamic programmable logic arrays

Wen-Ben Jone, Sunil R. Das, Jianxun Liu, 2006, IEEE Transactions on Instrumentation and Measurement.

Satellite system interference modeling (11.7-12.2 GHz)

Sunil R. Das, G. Sharp, 1976 .

PGEN: A Novel Approach to Sequential Circuit Test Generation

Sunil R. Das, Nigam Shah, Wen-Ben Jone, 1996, VLSI Design.

Getting errors to catch themselves - self-testing of VLSI circuits with built-in hardware

Sunil R. Das, 2005, IEEE Transactions on Instrumentation and Measurement.

Test set embedding based on width compression for mixed-mode BIST

Sunil R. Das, Krishnendu Chakrabarty, 1999, IMTC/99. Proceedings of the 16th IEEE Instrumentation and Measurement Technology Conference (Cat. No.99CH36309).

An efficient BIST method for non-traditional faults of embedded memory arrays

Wen-Ben Jone, Sunil R. Das, Der-Chen Huang, 2003, IEEE Trans. Instrum. Meas..

Space compaction under generalized mergeability

Sunil R. Das, Amiya Nayak, Mansour H. Assaf, 1998, IEEE Trans. Instrum. Meas..

Design of Aliasing Free Space Compressor in BIST with Maximal Compaction Ratio Using Concepts of Strong and Weak Compatibilities of Response Data Outputs and Generalized Sequence Mergeability

Sunil R. Das, Mansour H. Assaf, Emil M. Petriu, 2002, IWDC.

Cascade of two-input nonlinear logic in designing space compression networks in VLSI

Sunil R. Das, Voicu Groza, Mansour H. Assaf, 2012 .

Aliasing-Free Space Compaction in VLSI with Cascade of Two-Input OR/NOR Logic

Sunil R. Das, Voicu Groza, Altaf Hossain, 2011, 2011 Sixth IEEE International Symposium on Electronic Design, Test and Application.

Strong connectivity in symmetric graphs and generation of maximal minimally strongly connected subgraphs

Sunil R. Das, C. L. Sheng, C. L. Sheng, 1978, Inf. Sci..

A Novel Technique for Input Vector Compression in System-on-Chip Testing

Sunil R. Das, Mansour H. Assaf, Satyendra Biswas, 2008, 2008 International Conference on Information Technology.

TRANSITION MATRICES IN MULTIPLE PRESET EXPERIMENTS AND INITIAL STATE IDENTIFICATION OF SYNCHRONOUS SEQUENTIAL-MACHINES

Sunil R. Das, Zen Chen, Ping Chao, 1979 .

Promising ComplexASICDesign Verification Methodology

Sunil R. Das, Mansour H. Assaf, 2007 .

Aliasing-Free Compaction in Testing Cores-Based System-on-Chip (SoC) using Compatibility of Response Data outputs

Sunil R. Das, Mansour H. Assaf, Emil M. Petriu, 2004, Trans. SDPS.

CACOP-a random pattern testability analyzer

Wen-Ben Jone, Sunil R. Das, 1995, IEEE Trans. Syst. Man Cybern..

On testing of sequential machines using circuit decomposition and stochastic modeling

Wen-Ben Jone, Sunil R. Das, Amiya Nayak, 1995, IEEE Trans. Syst. Man Cybern..

JBits Implementation and Design Verification in Space Compressor Design of Digital Circuits

Sunil R. Das, Voicu Groza, Mansour H. Assaf, 2003, Modelling, Identification and Control.

An appraisal of the performance of the MMSC subgraph generation algorithm on a Cyber System 170/720

Sunil R. Das, S. Y. Lee, 2005, Computing.

Parity bit signature in response data compaction and built-in self-testing of VLSI circuits with nonexhaustive test sets

Wen-Ben Jone, Sunil R. Das, Krishnendu Chakrabarty, 2003, IEEE Trans. Instrum. Meas..

Data compression in space under generalized mergeability based on concepts of cover table and frequency ordering

Wen-Ben Jone, Sunil R. Das, Krishnendu Chakrabarty, 2002, IEEE Trans. Instrum. Meas..

Further studies on the matrix approach to the measurement and control problems of synchronous sequential machines—performance evaluation by computer simulation and application of specific heuristics

Sunil R. Das, Zen Chen, W. J Hsu, 1986 .

A parallel built-in self-diagnostic method for nontraditional faults of embedded memory arrays

Wen-Ben Jone, Sunil R. Das, Der-Cheng Huang, 2004, IEEE Transactions on Instrumentation and Measurement.

Test-set embedding based on width compression for mixed-mode BIST

Sunil R. Das, Krishnendu Chakrabarty, 2000, IEEE Trans. Instrum. Meas..

Memristor-Based High-Speed Memory Cell With Stable Successive Read Operation

Sunil R. Das, Satyendra N. Biswas, Mohammad Nazmus Sakib, 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

High speed S - box architecture for advanced encryption standard

Sunil R. Das, Satyendra N. Biswas, Scott Morton, 2013 .

Nontransient fault testing in sequential logic circuits using stochastic modeling and simulation

Sunil R. Das, Sunil R. Das, 1989 .

On random testing for combinational circuits with a high measure of confidence

Wen-Ben Jone, Sunil R. Das, 1992, IEEE Trans. Syst. Man Cybern..

Testing Analog and Mixed-Signal Circuits With Built-In Hardware—A New Approach

Wen-Ben Jone, Sunil R. Das, Amiya Nayak, 2007, IEEE Transactions on Instrumentation and Measurement.

An algorithm for generating prime implicants

Sunil R. Das, Voicu Groza, Mansour H. Assaf, 2016, 2016 IEEE International Instrumentation and Measurement Technology Conference Proceedings.

Transition matrices in the measurement and control of synchronous sequential machines

Sunil R. Das, Zen Chen, C. L. Sheng, 1979, Inf. Sci..

Random Pattern Testability Enhancement by Circuit Rewiring

Wen-Ben Jone, Sunil R. Das, Shih-Chieh Chang, 2001, VLSI Design.

An improved output compaction technique for built-in self-test in VLSI circuits

Wen-Ben Jone, Sunil R. Das, Amiya Nayak, 1995, Proceedings of the 8th International Conference on VLSI Design.

An adaptive compressed MPEG-2 video watermarking scheme

Sunil R. Das, Emil M. Petriu, Satyendra Biswas, 2005, IEEE Transactions on Instrumentation and Measurement.

A high performance dynamic logic with nMOS based resistive keeper circuit

Sunil R. Das, Satyendra N. Biswas, Kazi Fatima Sharif, 2017, 2017 IEEE Symposium on Computer Applications & Industrial Electronics (ISCAIE).

Guest Editorial

Sunil R. Das, 2001, VLSI Design.

An approach to microprogram optimization through bit dimension reduction in a given control store specification

Sunil R. Das, Zen Chen, C. L. Sheng, 1979 .