Soo Doo Chae

Line roughness improvements on self-aligned quadruple patterning by wafer stress engineering

Akiteru Ko, Kazuya Okubo, Eric Liu, 2018, Advanced Lithography.

Performance of AlGaSb/InAs TFETs With Gate Electric Field and Tunneling Direction Aligned

Rui Li, Soo Doo Chae, Qin Zhang, 2012, IEEE Electron Device Letters.

Transistors with chemically synthesized layered semiconductor WS2 exhibiting 105 room temperature modulation and ambipolar behavior

Soo Doo Chae, Wan Sik Hwang, Debdeep Jena, 2012, 1204.0474.

InAs/AlGaSb heterojunction tunnel field‐effect transistor with tunnelling in‐line with the gate field

Huili Grace Xing, Chen Chen, Rui Li, 2012 .