Kiyotaka Imai

发表

Line roughness improvements on self-aligned quadruple patterning by wafer stress engineering

Akiteru Ko, Kazuya Okubo, Eric Liu, 2018, Advanced Lithography.

A 400MHz 64bit BiCMOS ALU

Kiyotaka Imai, K Takida, H Okamura, 1995 .

A 100 nm Node CMOS Technology for System-on-a-Chip Applications

Kiyotaka Imai, A. Ono, 2002 .

1P1-E12 The discussion and construction of a data sharing system in the remote robot system using RTM

Yasuharu Kunii, Kiyotaka Imai, Takahiro Shinotsuka, 2008 .

Device technology for body biasing scheme

Kiyotaka Imai, Masahiro Ikeda, Yasushi Yamagata, 2005, 2005 IEEE International Symposium on Circuits and Systems.

Logic device scaling trend in ITRS 2007

Kiyotaka Imai, 2008, Photomask Japan.

Process integration technologies for sub-half micron BiCMOS LSls

Hiroshi Yoshida, Kiyotaka Imai, Y. Kinoshita, 1996 .

CMOS device optimization for system-on-a-chip applications

Kiyotaka Imai, K. Yamaguchi, K. Matsui, 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

A 5-11s l-Mb ECL BiCMOS SRAM

Masahide Takada, Kiyotaka Imai, Kazuyuki Nakamura, 1990 .

A 2-V, 1-10 GHz BiCMOS transceiver chip for multimode wireless communications networks

Kiyotaka Imai, T. Yamazaki, M. Madihian, 1997 .

「パズルコソセプト」 - CMOSに比較して消費電力 , 集積度 , コスト共に優れたLSIを提供するBiCMOS LSIのデザイソコソセプト - ( ＂ PUZZLE CONCEPT ＂ - A New BiCMOS LSI Design Concept Offering Lower Power , Higher Integration Density and Lower Cost Than CMOS - )

Kiyotaka Imai, 강촌균, 무전황일, 1996 .

A 100nm node CMOS technology for practical SOC application

Kiyotaka Imai, Michiya Takimoto, Yasuhisa Yamada, 2002 .

A novel sub-2.0 V BiCMOS logic circuit with a BiCMOS charge pump

Kiyotaka Imai, K. Takeda, Y. Kinoshita, 1994, Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting.

A Study on Large-Scale Wireless Mesh Networks Cooperating with High-Speed External Networks - Improvement of Performance Deterioration Due to Increasing Network Scale

Kiyotaka Imai, Hisao Yamamoto, 2010, 2010 International Conference on Cyber-Enabled Distributed Computing and Knowledge Discovery.

B-21-12 A study on load-balancing with alternate route control in wireless mesh networks

Kiyotaka Imai, Hisao Yamamoto, 2010 .

2.0 V BiCM S Logic Circ

Kiyotaka Imai, Y. Kinoshita, Koichi Takeda, 1996 .

s, 1 W, 2.5 V, 32 Kb TL-CMOS SRAM Macro with OS Access Transistors

Satoshi Nakamura, Masahide Takada, Kiyotaka Imai, 1995 .

A unified MOSFET channel charge model for device modeling in circuit simulation

Yuhua Cheng, Kiyotaka Imai, Chenming Hu, 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Low Standby Power CMOS Process Integration Scheme for 45-32 nm node

Kiyotaka Imai, 2007 .

A 5 ns 1 Mb BiCMOS SRAM with ECL I/O interface

Masahide Takada, T. Yamazaki, Kiyotaka Imai, 1990, IEEE International Symposium on Circuits and Systems.

Study of Automatic Bit Line voltage Swing controller for SRAMs

Hiroshi Yoshida, Kiyotaka Imai, Y. Kinoshita, 1995 .

Studies of Coulomb Blockade , Single-Trangister Dynamic Memory , and Oxide Trap Charge State Based on the Random Telegraph Noise Modeling

Kiyotaka Imai, Chenming Hu, Shiro Kamohara, 1997 .

Position sensing on sphere surface using machine learning

Kiyotaka Imai, Hashizume Yoichiro, Okamura Soichiro, 2019 .

Merits of CMOS/SIMOX technology for low-voltage SRAM macros : Special Issue on Advanced Memory Devices and Technologies

Kiyotaka Imai, Kouichi Kumagai, Hiroaki Iwaki, 1999 .

A 1 ns, 1 W, 2.5 V, 32 Kb NTL-CMOS SRAM macro using a memory cell with p-channel access transistors

Kiyotaka Imai, Hiroshi Yoshida, K. Takeda, 1995 .

Local lattice strain distribution around a transistor channel in metal–oxide–semiconductor devices

Kiyotaka Imai, Haruhiko Ono, Nobuyuki Ikarashi, 2001 .

A 65nm-node LSTP(LOW Standby Power) Poly-Si/a-Si/HfSiON Transistor with High Ion-Istandby Ratio and Reliability

Kiyotaka Imai, Toru Tatsumi, T. Iwamoto, 2004 .

Process integration technology for sub-30 ps ECL BiCMOS using heavily boron doped epitaxial contact (HYDEC)

Kiyotaka Imai, Y. Kinoshita, T. Yamazaki, 1994, Proceedings of 1994 IEEE International Electron Devices Meeting.

A 70 nm gate length CMOS technology with 1.0 V operation

T. Fukai, Kiyotaka Imai, A. Ono, 2000, 2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104).

A new SRAM cell design using 0.35 /spl mu/m CMOS/SIMOX technology

Kiyotaka Imai, Kouichi Kumagai, Hiroaki Iwaki, 1997, 1997 IEEE International SOI Conference Proceedings.

A Premetal BPSG Filled Deep Trench Isolation Technology for ECL-BiCMOS LSIs using CMP

Mohammad Madihian, Kiyotaka Imai, Tohru Yamazaki, 1995, ESSDERC '95: Proceedings of the 25th European Solid State Device Research Conference.

A sub-2.0 V BiCMOS logic circuit with a BiCMOS charge pump

Kiyotaka Imai, Y. Kinoshita, M. Takada, 1996, IEEE J. Solid State Circuits.

A 0.99-/spl mu/m/sup 2/ loadless four-transistor SRAM cell in 0.13-/spl mu/m generation CMOS technology

Kiyotaka Imai, T. Tamura, Yoshiaki Yamada, 2000, 2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104).

A 0.10 /spl mu/m CMOS, 1.2 V, 2 GHz phase-locked loop with gain compensation VCO

Kiyotaka Imai, Masayuki Mizuno, Masakazu Yamashina, 2001, Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169).