Enric Musoll

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Predicting the usefulness of a block result: a micro-architectural technique for high-performance low-power processors

Enric Musoll, 1999, MICRO-32. Proceedings of the 32nd Annual ACM/IEEE International Symposium on Microarchitecture.

Load balancing packets on a tile-based massive multi-core processor with S-NUCA

Enric Musoll, 2010, 2010 ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS).

High-level synthesis techniques for reducing the activity of functional units

Jordi Cortadella, Enric Musoll, 1995, ISLPED '95.

Working-zone encoding for reducing the energy in microprocessor address buses

Tomás Lang, Jordi Cortadella, Enric Musoll, 1998, IEEE Trans. Very Large Scale Integr. Syst..

Speculating to reduce unnecessary power consumption

Enric Musoll, 2003, TECS.

Exploiting the locality of memory references to reduce the address bus energy

Tomás Lang, Jordi Cortadella, Enric Musoll, 1997, Proceedings of 1997 International Symposium on Low Power Electronics and Design.

Design Space Exploration of High-Performance Parallel Architectures

Mario Nemirovsky, Enric Musoll, 2008 .

Extension of the working-zone-encoding method to reduce the energy on the microprocessor data bus

Tomás Lang, Jordi Cortadella, Enric Musoll, 1998, Proceedings International Conference on Computer Design. VLSI in Computers and Processors (Cat. No.98CB36273).

Variable-size mosaics: A process-variation aware technique to increase the performance of tile-based, massive multi-core processors

Enric Musoll, 2011, Comput. Electr. Eng..

Jordi Cortadella, Enric Musoll, 1998, Integr. Comput. Aided Eng..

A Massively Multithreaded Packet Processor

Mario Nemirovsky, Enric Musoll, Rodolfo A. Milito, 2004 .

Power Gating Clustered Many-Core Architectures

Enric Musoll, 2008, J. Low Power Electron..

A Process-Variation Aware Technique for Tile-Based, Massive Multicore Processors

Enric Musoll, 2009, IEEE Computer Architecture Letters.

Leakage-saving opportunities in mesh-based massive multi-core architectures

Enric Musoll, 2010, CARN.

Energy and thermal tradeoffs in hardware-based load balancing for clustered multi-core architectures implementing power gating

Enric Musoll, 2008, 2008 Symposium on Application Specific Processors.

Trading off higher execution latency for increased reliability in tile-based massive multi-core architectures

Enric Musoll, 2009, 2009 10th International Symposium on Quality Electronic Design.

A cost-effective load-balancing policy for tile-based, massive multi-core packet processors

Enric Musoll, 2010, TECS.

Low-Power Array Multipliers with Transition-Retaining Barriers

Enric Musoll, Jordi Cortadella, 1995 .

Hardware-Based Load Balancing for Massive Multicore Architectures Implementing Power Gating

Enric Musoll, 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Scheduling and resource binding for low power

Jordi Cortadella, Enric Musoll, J. Cortadella, 1995, Proceedings of the Eighth International Symposium on System Synthesis.

Mesh-based many-core performance under process variations: a core yield perspective

Enric Musoll, 2010, CARN.

Individual flip-flops with gated clocks for low power datapaths

Tomás Lang, Jordi Cortadella, Enric Musoll, 1997 .

A Thermal-Friendly Load-Balancing Technique for Multi-Core Processors

Enric Musoll, 2008, 9th International Symposium on Quality Electronic Design (isqed 2008).

Optimizing CMOS circuits for low power using transistor reordering

Jordi Cortadella, Enric Musoll, 1996, Proceedings ED&TC European Design and Test Conference.