S. Theoharis

Low-power design of array architectures

Dimitrios Soudris, G. Theodoridis, Adonios Thanailakis, 1996, Proceedings of Third International Conference on Electronics, Circuits, and Systems.

0.6 [micro sign]m CMOS, 622/155 Mbit/s ATM-SDH/SONET framer IC

A. Birbas, S. Theoharis, M. Koziotis, 1999 .

Accurate data path models for fast RT-level power estimation

G. Theodoridis, Constantinos E. Goutis, P. Merakos, 2000 .

A novel approach for reducing the switching activity in two-level logic circuits

Dimitrios Soudris, G. Theodoridis, Constantinos E. Goutis, 1996, Proceedings of Third International Conference on Electronics, Circuits, and Systems.

Run-Time Power Management for Low and Medium Bit-Rate Digital Receivers

Dimitrios Soudris, Costas E. Goutis, S. Theoharis, 2000 .

Quantizing the 9/7 Daubechies filter coefficients for 2D DWT VLSI implementations

N. D. Zervas, S. Theoharis, V. Spiliotopoulos, 2002, 2002 14th International Conference on Digital Signal Processing Proceedings. DSP 2002 (Cat. No.02TH8628).

Low power synthesis of sum-of-products computation

Thanos Stouraitis, Kostas Masselos, Constantinos E. Goutis, 2000, ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514).

Switching activity estimation under real-gate delay using timed Boolean functions

Dimitrios Soudris, George Theodoridis, Constantinos E. Goutis, 2000 .

“ Accurate And Fast Power Estimation Of Large Combinational Circuits ”

G. Theodoridis, C. Goutis, S. Theoharis, 1999 .