S. Kubicek

发表

Optimization of nMOS high-frequency transistor characteristics for application in MMICs

D. Schreurs, B. Nauwelaers, K. De Meyer, 1998, 1998 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems. Digest of Papers (Cat. No.98EX271).

Analytical calculations of a figure of merit for novel MOSFET architecture for the sub 0.25 /spl mu/m range

K. De Meyer, S. Kubicek, S. Biesemans, 1994, Proceedings of International Workshop on Numerical Modeling of processes and Devices for Integrated Circuits: NUPAD V.

Device and circuit-level analog performance trade-offs: a comparative study of planar bulk FETs versus FinFETs

P. Wambacq, B. Parvais, A. Mercha, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

Modelling mobility degradation due to remote Coulomb scattering from dielectric charges and its impact on MOS device performance

Stefan De Gendt, Wim Magnus, Kristin De Meyer, 2005, Microelectron. Reliab..

Accurate prediction of device performance in sub-10nm WFIN FinFETs using scalpel SSRM-based calibration of process simulations

P. Eyben, D. Mocuta, J. Mitard, 2016, 2016 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD).

Towards high performance sub-10nm finW bulk FinFET technology

Naoto Horiguchi, Jérôme Mitard, P. Eyben, 2016, 2016 46th European Solid-State Device Research Conference (ESSDERC).

Planar Bulk MOSFETs Versus FinFETs: An Analog/RF Perspective

A. Mercha, S. Decoutere, S. Donnay, 2006, IEEE Transactions on Electron Devices.

Migrating from planar to FinFET for further CMOS scaling: SOI or bulk?

R. Rooyackers, Liesbeth Witters, C. Ortolland, 2009, 2009 Proceedings of ESSCIRC.

Spice simulation of 0.18 /spl mu/m CMOS ring oscillators using physical models for capacitance and series resistance

S. Biesemans, K. De Meyer, S. Kubicek, 1997, International Electron Devices Meeting. IEDM Technical Digest.

New architectures for deep submicron MOSFETs

S. Biesemans, K. De Meyer, S. Kubicek, 1998, 28th European Solid-State Device Research Conference.

Evidences of anodic-oxidation reset mechanism in TiN\NiO\Ni RRAM cells

R. Degraeve, L. Goux, B. Govoreanu, 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

Improvement of the CMOS characteristics of bulk Si FinFETs by high temperature ion implantation

D. Mocuta, R. Ritzenthaler, N. Horiguchi, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

Work function of Ni silicide phases on HfSiON and SiO/sub 2/: NiSi, Ni/sub 2/Si, Ni/sub 31/Si/sub 12/, and Ni/sub 3/Si fully silicided gates

C. Vrancken, A. Veloso, S. Biesemans, 2006, IEEE Electron Device Letters.

Laser-annealed junctions with advanced CMOS gate stacks for 32nm Node: Perspectives on device performance and manufacturability

C. Ortolland, T. Chiarella, W. Vandervorst, 2008, 2008 Symposium on VLSI Technology.

Impact of MOSFET oxide breakdown on digital circuit operation and reliability

E. Vandamme, R. Degraeve, B. Kaczer, 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

Investigation of intrinsic transistor performance of advanced CMOS devices with 2.5 nm NO gate oxides

L. Deferm, P. Jansen, D. Kerr, 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

Novel process to pattern selectively dual dielectric capping layers using soft-mask only

A. Akheyar, T. Chiarella, C. Vrancken, 2008, 2008 Symposium on VLSI Technology.

Interface passivation mechanisms in metal gated oxide capacitors

S. De Gendt, M. Heyns, T. Schram, 2004, Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850).

Scalability of Ni FUSI gate processes: phase and Vt control to 30 nm gate lengths

T. Chiarella, C. Vrancken, A. Veloso, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

CMP-less integration of fully Ni-silicided metal gates in FinFETs by simultaneous silicidation of the source, drain, and the gate using a novel dual hard mask approach

R. Rooyackers, B. Kaczer, S. Locorotondo, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

Dual Work Function Phase Controlled Ni-FUSI CMOS (NiSi NMOS, Ni2Si or Ni31Si12 PMOS): Manufacturability, Reliability & Process Window Improvement by Sacrificial SiGe Cap

S. Locorotondo, H. Bender, T. Chiarella, 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

Low VT CMOS using doped Hf-based oxides, TaC-based Metals and Laser-only Anneal

S. De Gendt, S. Van Elshocht, A. Akheyar, 2007, 2007 IEEE International Electron Devices Meeting.

On the impact of indium and boron on the Reversed Narrow-Channel Effect (RNCE) in BULK and SOI MOSFETs

S. Kubicek, Jeongho Lyu, A. van Meer, 1999, 1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453).

Limitations of shift-and-ratio based L/sub eff/ extraction techniques for MOS transistors with halo or pocket implants

N. Collaert, M. Rosmeulen, K. De Meyer, 2000, IEEE Electron Device Letters.

Low Vt Ni-FUSI CMOS Technology using a DyO cap layer with either single or dual Ni-phases

S. Van Elshocht, P. Lehnen, C. Vrancken, 2007, 2007 IEEE Symposium on VLSI Technology.

Moving Spins From Lab to Fab: A Silicon-Based Platform for Quantum Computing Device Technologies

B. Govoreanu, D. Mocuta, Ts. Ivanov, 2019, 2019 Silicon Nanoelectronics Workshop (SNW).

CMOS scaling to 25 nm gate lengths

K. De Meyer, S. Kubicek, 2002, The Fourth International Conference on Advanced Semiconductor Devices and Microsystem.

Barrier permeation effects on the inversion layer subband structure and its applications to the electron mobility

K. De Meyer, Wim Magnus, M. Heyns, 2005 .

Demonstration of fully Ni-silicided metal gates on HfO/sub 2/ based high-k gate dielectrics as a candidate for low power applications

E. Augendre, A. Veloso, S. Biesemans, 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..

A manufacturable 25 nm planar MOSFET technology

J. Bolk, S. Kubicek, C.J.J. Dachs, 2001, 2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184).

Multiphysics Simulation & Design of Silicon Quantum Dot Qubit Devices

B. Govoreanu, G. Eneman, A. Spessot, 2019, 2019 IEEE International Electron Devices Meeting (IEDM).

CMOS integration of dual work function phase controlled Ni FUSI with simultaneous silicidation of NMOS (NiSi) and PMOS (Ni-rich silicide) gates on HfSiON

S. Locorotondo, T. Chiarella, C. Vrancken, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..