Yinhe Han

发表

Response compaction for test time and test pins reduction based on advanced convolutional codes

Xiaowei Li, Huawei Li, Yu Hu, 2004 .

Deterministic and low power BIST based on scan slice overlapping

Xiaowei Li, Ji Li, Yinhe Han, 2005, 2005 IEEE International Symposium on Circuits and Systems.

On predicting NBTI-induced circuit aging by isolating leakage change

Qiang Xu, Xiaowei Li, Song Jin, 2013, International Symposium on Quality Electronic Design (ISQED).

Response compaction for system-on-a-chip based on advanced convolutional codes

Huawei Li, Xiaowei Li, Yinhe Han, 2006, Science in China Series F: Information Sciences.

A New Multiple-Round Dimension-Order Routing for Networks-on-Chip

Huawei Li, Xiaowei Li, Yinhe Han, 2011, IEICE Trans. Inf. Syst..

Performance-asymmetry-aware topology virtualization for defect-tolerant NoC-based many-core processors

Xiaowei Li, Yue Yu, Shangping Ren, 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

SoC Leakage Power Reduction Algorithm by Input Vector Control

Zhimin Zhang, Dongrui Fan, Yinhe Han, 2005, 2005 International Symposium on System-on-Chip.

Enabling Near-Threshold Voltage(NTV) operation in Multi-VDD cache for power reduction

Huawei Li, Xiaowei Li, Yinhe Han, 2013, 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013).

Validation analysis and test flow optimization of VLSI chip

Xiaowei Li, Yinhe Han, Yanzhuo Tan, 2005, 2005 IEEE International Symposium on Circuits and Systems.

Frequency Analysis Method for Propagation of Transient Errors in Combinational Logic

Xiaowei Li, Yinhe Han, Shaohua Lei, 2007, 16th Asian Test Symposium (ATS 2007).

Thread: Towards fine-grained precision reconfiguration in variable-precision neural network accelerator

Yujie Wang, Ying Wang, Yinhe Han, 2019, IEICE Electron. Express.

CNN-based object detection solutions for embedded heterogeneous multicore SoCs

Cheng Wang, Xiaowei Li, Yinhe Han, 2017, 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC).

SmartCap: User experience-oriented power adaptation for smartphone's application processor

Xiaowei Li, Yinhe Han, Xueliang Li, 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Simultaneous Reduction of Test Data Volume and Testing Power for Scan-Based Test

Xiaowei Li, Yinhe Han, 2004, ESA/VLSI.

A clustering-based scheme for concurrent trace in debugging NoC-based multicore systems

Xiaowei Li, Jianxin Wang, Yinhe Han, 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

P^(2)CLRAF: An Pre- and Post-Silicon Cooperated Circuit Lifetime Reliability Analysis Framework

Huawei Li, Xiaowei Li, Song Jin, 2010, 2010 19th IEEE Asian Test Symposium.

Test resource partitioning based on efficient response compaction for test time and tester channels reduction

Huawei Li, Xiaowei Li, Yongjun Xu, 2003, 2003 Test Symposium.

Defect Tolerance in Homogeneous Manycore Processors Using Core-Level Redundancy with Unified Topology

Qiang Xu, Xiaowei Li, Yinhe Han, 2008, 2008 Design, Automation and Test in Europe.

On optimizing system energy of multi-core SoCs based on dynamically reconfigurable voltage-frequency island

Songwei Pei, Huawei Li, Song Jin, 2015, VLSI Design, Automation and Test(VLSI-DAT).

System-level hardware failure prediction using deep learning

Krishnendu Chakrabarty, Bing Zhao, Yinhe Han, 2019, 2019 56th ACM/IEEE Design Automation Conference (DAC).

Wrapper Scan Chains Design for Rapid and Low Power Testing of Embedded Cores

Yu Hu, Huawei Li, Xiaowei Li, 2005, IEICE Trans. Inf. Syst..

A resilient on-chip router design through data path salvaging

Xiaowei Li, Yinhe Han, Cheng Liu, 2011, 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011).

M-IVC: Applying multiple input vectors to co-optimize aging and leakage

Song Jin, Yinhe Han, 2012, Microelectron. J..

FlexFlow: A Flexible Dataflow Accelerator Architecture for Convolutional Neural Networks

Xiaowei Li, Yinhe Han, Jiajun Li, 2017, 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA).

An Analytical Framework for Estimating Scale-Out and Scale-Up Power Efficiency of Heterogeneous Manycores

Xiaowei Li, Jun Ma, Yinhe Han, 2016, IEEE Transactions on Computers.

Exploiting the Potential of Computation Reuse Through Approximate Computing

Xin He, Xiaowei Li, Yinhe Han, 2017, IEEE Transactions on Multi-Scale Computing Systems.

Address Remapping for Static NUCA in NoC-Based Degradable Chip-Multiprocessors

Huawei Li, Xiaowei Li, Yinhe Han, 2010, 2010 IEEE 16th Pacific Rim International Symposium on Dependable Computing.

ApproxEye: Enabling approximate computation reuse for microrobotic computer vision

Xin He, Xiaowei Li, Yinhe Han, 2017, 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC).

A Novel Post-Silicon Debug Mechanism Based on Suspect Window

Xiaowei Li, Yinhe Han, Jianliang Gao, 2010, IEICE Trans. Inf. Syst..

Eliminating data invalidation in debugging multiple-clock chips

Xiaowei Li, Yinhe Han, Jianliang Gao, 2011, 2011 Design, Automation & Test in Europe.

A Scalable Scan Architecture for Godson-3 Multicore Microprocessor

Hui Liu, Huawei Li, Xiangku Li, 2009, 2009 Asian Test Symposium.

A Cost-Effective Energy Optimization Framework of Multicore SoCs Based on Dynamically Reconfigurable Voltage-Frequency Islands

Songwei Pei, Huawei Li, Song Jin, 2016, TODE.

Economizing TSV Resources in 3-D Network-on-Chip Design

Lei Zhang, Huawei Li, Xiaowei Li, 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Response compaction for test time and test pins reduction based on advanced convolutional codes

Yu Hu, Huawei Li, Xiaowei Li, 2004, 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2004. DFT 2004. Proceedings..

VANUCA:大容量キャッシュにおける近閾値電圧動作【Powered by NICT】

Ying Wang, Yinhe Han, Huawei Li, 2016 .

Flex memory: Exploiting and managing abundant off-chip optical bandwidth

Huawei Li, Xiaowei Li, Yinhe Han, 2011, 2011 Design, Automation & Test in Europe.

Performance-Driven Crosstalk Mitigation Based on Bus-Grouping Transmission

Hui Liu, Yinhe Han, Xiaowei Li, 2007 .

BAT: Performance-Driven Crosstalk Mitigation Based on Bus-Grouping Asynchronous Transmission

Hui Liu, Xiaowei Li, Yinhe Han, 2008, IEICE Trans. Electron..

Dadu-P: A Scalable Accelerator for Robot Motion Planning in a Dynamic Environment

Yinhe Han, Ying Wang, Xiaoming Chen, 2018, 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC).

Wear rate leveling: Lifetime enhancement of PRAM with endurance variation

Xiaowei Li, Yinhe Han, Ying Wang, 2011, 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC).

Accelerating Lightpath setup via broadcasting in binary-tree waveguide in Optical NoCs

Huawei Li, Xiaowei Li, Yinhe Han, 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

A unified online Fault Detection scheme via checking of Stability Violation

Xiaowei Li, Yinhe Han, Guihai Yan, 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

Dadu: Accelerating Inverse Kinematics for high-DOF robots

Xiaowei Li, Ninghui Sun, Yinhe Han, 2017, 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC).

Leakage Current Optimization Techniques During Test Based on Don’t Care Bits Assignment

Wei Wang, Xiaowei Li, Yu Hu, 2007, Journal of Computer Science and Technology.

The Abacus Turn Model

Yinhe Han, Binzhang Fu, Xiaowei Li, 2014 .

Test-Quality Optimization for Variable $n$ -Detections of Transition Faults

Huawei Li, Xiaowei Li, Kwang-Ting Cheng, 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Wrapper Chain Design for Testing TSVs Minimization in Circuit-Partitioned 3D SoC

Xiaowei Li, Jun Liu, Yinhe Han, 2011, 2011 Asian Test Symposium.

C-Brain: A deep learning accelerator that tames the diversity of CNNs through adaptive data-level parallelization

Xiaowei Li, Xin Zhao, Yinhe Han, 2016, 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC).

VANUCA: Enabling Near-Threshold Voltage Operation in Large-Capacity Cache

Huawei Li, Xiaowei Li, Yinhe Han, 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

An on-chip combinational decompressor for reducing test data volume

Yu Hu, Xiaowei Li, Yinhe Han, 2006, 2006 IEEE International Symposium on Circuits and Systems.

RT3D: Real-Time 3-D Vehicle Detection in LiDAR Point Cloud for Autonomous Driving

Jing Ye, Ninghui Sun, Yinhe Han, 2018, IEEE Robotics and Automation Letters.

T2- TAM:Reusing infrastructure resource to provide parallel testing for NoC based Chip

Huawei Li, Yinhe Han, Xiaowei Li, 2009, 2009 IEEE 8th International Conference on ASIC.

RISO: Relaxed network-on-chip isolation for cloud processors

Xiaowei Li, Yinhe Han, Binzhang Fu, 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).

Pair balance-based test scheduling for SOCs

Yu Hu, Huawei Li, Xiaowei Li, 2004, 13th Asian Test Symposium.

A case of precision-tunable STT-RAM memory design for approximate neural network

Huawei Li, Xiaowei Li, Yinhe Han, 2015, 2015 IEEE International Symposium on Circuits and Systems (ISCAS).

Communication Lower Bound in Convolution Accelerators

Yu Wang, Xiaoming Chen, Yinhe Han, 2019, International Symposium on High-Performance Computer Architecture.

nGFSIM : A GPU-based fault simulator for 1-to-n detection and its applications

Huawei Li, Xiaowei Li, Kwang-Ting Cheng, 2010, 2010 IEEE International Test Conference.

SmartCap: Using Machine Learning for Power Adaptation of Smartphone's Application Processor

Yinhe Han, Xueliang Li, Xiaowei Li, 2014, TODE.

Rapid and energy-efficient testing for embedded cores

Yu Hu, Huawei Li, Xiaowei Li, 2004, 13th Asian Test Symposium.

A New Post-Silicon Debug Approach Based on Suspect Window

Xiaowei Li, Yinhe Han, Jianliang Gao, 2009, 2009 27th IEEE VLSI Test Symposium.

SVFD: A Versatile Online Fault Detection Scheme via Checking of Stability Violation

Xiaowei Li, Yinhe Han, Guihai Yan, 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Fast algorithm for leakage power reduction by input vector control

Dongrui Fan, Xiaowei Li, Yinhe Han, 2005, 2005 6th International Conference on ASIC.

RISO: Enforce Noninterfered Performance With Relaxed Network-on-Chip Isolation in Many-Core Cloud Processors

Xiaowei Li, Yinhe Han, Ying Wang, 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

PSI Conscious Write Scheduling: Architectural Support for Reliable Power Delivery in 3-D Die-Stacked PCM

Lei Zhang, Huawei Li, Xiaowei Li, 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

ProPRAM: Exploiting the transparent logic resources in Non-Volatile Memory for Near Data Computing

Huawei Li, Xiaowei Li, Yinhe Han, 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).

A New Multiple-Round DOR Routing for 2D Network-on-Chip Meshes

Huawei Li, Xiaowei Li, Yinhe Han, 2009, 2009 15th IEEE Pacific Rim International Symposium on Dependable Computing.

DimRouter: A Multi-Mode Router Architecture for Higher Energy-Proportionality of On-Chip Networks

Ying Wang, Yinhe Han, Shiqi Lian, 2018, Journal of Computer Science and Technology.

STT-RAM Buffer Design for Precision-Tunable General-Purpose Neural Network Accelerator

Ying Wang, Yinhe Han, Xiaowei Li, 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

DISCO: A low overhead in-network data compressor for energy-efficient chip multi-processors

Jun Zhou, Huawei Li, Xiaowei Li, 2016, 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC).

MicroFix: exploiting path-grained timing adaptability for improving power-performance efficiency

Xiaowei Li, Hui Liu, Yinhe Han, 2009, ISLPED.

A General-Purpose Many-Accelerator Architecture Based on Dataflow Graph Clustering of Applications

Lei Zhang, Peng Chen, Yinhe Han, 2014, Journal of Computer Science and Technology.

Statistical lifetime reliability optimization considering joint effect of process variation and aging

Huawei Li, Xiaowei Li, Song Jin, 2011, Integr..

Embedded test resource for SoC to reduce required tester channels based on advanced convolutional codes

Huawei Li, Xiaowei Li, Yinhe Han, 2006, IEEE Transactions on Instrumentation and Measurement.

Scan Data Volume Reduction Using Periodically Alterable MUXs Decompressor

Yu Hu, Xiaowei Li, Yinhe Han, 2005, 14th Asian Test Symposium (ATS'05).

Statistical energy optimization on voltage-frequency island based MPSoCs in the presence of process variations

Songwei Pei, Song Jin, Yinhe Han, 2016, Microelectron. J..

Variation-Aware Scheduling for Chip Multiprocessors with Thread Level Redundancy

Xiaowei Li, Yinhe Han, Lei Zhang, 2009, 2009 15th IEEE Pacific Rim International Symposium on Dependable Computing.

A retrospective evaluation of energy-efficient object detection solutions on embedded devices

Ying Wang, Huawei Li, Yinhe Han, 2018, 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE).

TSV Minimization for Circuit — Partitioned 3D SoC Test Wrapper Design

Lei Zhang, Xiaowei Li, Yinhe Han, 2013, Journal of Computer Science and Technology.

A Low Overhead In-Network Data Compressor for the Memory Hierarchy of Chip Multiprocessors

Huawei Li, Yinhe Han, Xiaowei Li, 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Power and Area Efficient FPGA Building Blocks Based on Ferroelectric FETs

Michael T. Niemier, Xiaobo Sharon Hu, Suman Datta, 2019, IEEE Transactions on Circuits and Systems I: Regular Papers.

RADAR: a case for retention-aware DRAM assembly and repair in future FGR DRAM memory

Cheng Wang, Huawei Li, Xiaowei Li, 2015, DAC.

SuperRange: Wide operational range power delivery design for both STV and NTV computing

Xin He, Xiaowei Li, Yinhe Han, 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Dadu-P: a scalable accelerator for robot motion planning in a dynamic environment

Ying Wang, Xiaoming Chen, Yinhe Han, 2018, DAC.

ShuttleNoC: Boosting on-chip communication efficiency by enabling localized power adaptation

Xiaowei Li, Yinhe Han, Ying Wang, 2015, The 20th Asia and South Pacific Design Automation Conference.

Simulate-the-hardware: training accurate binarized neural networks for low-precision neural accelerators

Ying Wang, Jiajun Li, Xiaowei Li, 2019, ASP-DAC.

Co-optimization for test data compression and testing power based on variable-tail code

Xiaowei Li, Yongjun Xu, Yinhe Han, 2003, ASICON 2003.

Compression/Scan Co-design for Reducing Test Data Volume, Scan-in Power Dissipation, and Test Application Time

Yu Hu, Huawei Li, Xiaowei Li, 2006, IEICE Trans. Inf. Syst..

PIMSim: A Flexible and Detailed Processing-in-Memory Simulator

Xiaoming Chen, Xuehai Qian, Yinhe Han, 2019, IEEE Computer Architecture Letters.

ACR: Enabling computation reuse for approximate computing

Xin He, Xiaowei Li, Yinhe Han, 2016, 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC).

Wide Operational Range Processor Power Delivery Design for Both Super-Threshold Voltage and Near-Threshold Voltage Computing

Xin He, Xiao-Wei Li, Yinhe Han, 2016, Journal of Computer Science and Technology.

Thermal-Constrained Task Allocation for Interconnect Energy Reduction in 3-D Homogeneous MPSoCs

Xiaowei Li, Yinhe Han, Lei Zhang, 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

ZoneDefense: A Fault-Tolerant Routing for 2-D Meshes Without Virtual Channels

Huawei Li, Xiaowei Li, Yinhe Han, 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Fast Packet Classification using Group Bit Vector

Yinhe Han, Tong Liu, Xiaowei Li, 2006 .

A low power DRAM refresh control scheme for 3D memory cube

Huawei Li, Yinhe Han, Ying Wang, 2014, 2014 IEEE COOL Chips XVII.

On Topology Reconfiguration for Defect-Tolerant NoC-Based Homogeneous Manycore Systems

Qiang Xu, Huawei Li, Xiaowei Li, 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Fault tolerance mechanism in chip many-core processors

Lei Zhang, Huawei Li, Yinhe Han, 2007 .

Vertical interconnects squeezing in symmetric 3D mesh Network-on-Chip

Xiaowei Li, Cheng Liu, Yinhe Han, 2011, 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011).

Performance-asymmetry-aware scheduling for Chip Multiprocessors with static core coupling

Xiaowei Li, Yinhe Han, Lei Zhang, 2010, J. Syst. Archit..

AgileRegulator: A hybrid voltage regulator scheme redeeming dark silicon for power efficiency in a multicore architecture

Minyi Guo, Xiaowei Li, Yinhe Han, 2012, IEEE International Symposium on High-Performance Comp Architecture.

Embedded Test Decompressor to Reduce the Required Channels and Vector Memory of Tester for Complex Processor Circuit

Yu Hu, Huawei Li, Xiaowei Li, 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

PowerCap: Leverage Performance-Equivalent Resource Configurations for power capping

Huawei Li, Jun Ma, Yinhe Han, 2016, 2016 Seventh International Green and Sustainable Computing Conference (IGSC).

Variation-aware statistical energy optimization on voltage-frequency island based MPSoCs under performance yield constraints

Songwei Pei, Song Jin, Yinhe Han, 2014, 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC).

NXG05-4: Fast Packet Classification using Group Bit Vector

Tong Liu, Huawei Li, Xiaowei Li, 2006, IEEE Globecom 2006.

Extended Selective Encoding of Scan Slices for Reducing Test Data and Test Power

Xiaowei Li, Jun Liu, Yinhe Han, 2010 .

EcoUp: Towards Economical Datacenter Upgrading

Xiaowei Li, Jun Ma, Yinhe Han, 2016, IEEE Transactions on Parallel and Distributed Systems.

Using MUXs network to hide bunches of scan chains

Yu Hu, Huawei Li, Xiaowei Li, 2005, Sixth international symposium on quality electronic design (isqed'05).

Leveraging the core-level complementary effects of PVT variations to reduce timing emergencies in multi-core processors

Xiaowei Li, Yinhe Han, Xiaoyao Liang, 2010, ISCA '10.

Theoretic analysis and enhanced X-tolerance of test response compact based on convolutional code

Yu Hu, Huawei Li, Xiaowei Li, 2005, ASP-DAC.

A Thermal-Aware Parallel Multicast Testing Method Based on Many-Core Chips: A Thermal-Aware Parallel Multicast Testing Method Based on Many-Core Chips

Xiaowei Li, Fang Fang, Yinhe Han, 2010 .

Extended Selective Encoding of Scan Slices for Reducing Test Data and Test Power

Xiaowei Li, Jun Liu, Yinhe Han, 2009, 2009 Asian Test Symposium.

Addressing the issue of processing element under-utilization in general-purpose systolic deep learning accelerators

Ying Wang, Jiajun Li, Xiaoming Chen, 2019, ASP-DAC.

Fast algorithm for leakage power reduction by input vector control

Dongrui Fan, Yinhe Han, Xiaowei Li, 2005 .

Test Resource Partitioning Based on Efficient Response Compaction for Test Time and Tester Channels Reduction

Huawei Li, Xiaowei Li, Yinhe Han, 2005, Journal of Computer Science and Technology.

AnOn-chip Combinational Decompressor forReducing TestDataVolume

Xiaowei Li, Yinhe Han, Xiaowei Li, 2006 .

M-IVC: Using Multiple Input Vectors to Minimize Aging-Induced Delay

Huawei Li, Xiaowei Li, Song Jin, 2009, 2009 Asian Test Symposium.

Enhanced Wear-Rate Leveling for PRAM Lifetime Improvement Considering Process Variation

Xiaowei Li, Yinhe Han, Ying Wang, 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

MicroFix: Using timing interpolation and delay sensors for power reduction

Hui Liu, Xiaowei Li, Yinhe Han, 2011, TODE.

RevivePath: Resilient Network-on-Chip Design Through Data Path Salvaging of Router

Lei Zhang, Xiaowei Li, Cheng Liu, 2013, Journal of Computer Science and Technology.

moDNN: Memory Optimal Deep Neural Network Training on Graphics Processing Units

Xiaoming Chen, Xiaobo Sharon Hu, Yinhe Han, 2019, IEEE Transactions on Parallel and Distributed Systems.

Unified Capture Scheme for Small Delay Defect Detection and Aging Prediction

Huawei Li, Xiaowei Li, Song Jin, 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Merging Everything (ME): A Unified FPGA Architecture Based on Logic-in-Memory Techniques

Xiaoming Chen, Yinhe Han, Longxiang Yin, 2019, 2019 56th ACM/IEEE Design Automation Conference (DAC).

CuckooPIM: an efficient and less-blocking coherence mechanism for processing-in-memory systems

Ying Wang, Xiaoming Chen, Xiaowei Li, 2019, ASP-DAC.

PIMCH: Cooperative memory prefetching in processing-in-memory architecture

Ying Wang, Sheng Xu, Yinhe Han, 2018, 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC).

Data-aware DRAM refresh to squeeze the margin of retention time in hybrid memory cube

Huawei Li, Xiaowei Li, Yinhe Han, 2014, 2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

A signal degradation reduction method for memristor ratioed logic (MRL) gates

Xiaowei Li, Yinhe Han, Ying Wang, 2015, IEICE Electron. Express.

Reinventing Memory System Design for Many-Accelerator Architecture

Huawei Li, Yinhe Han, Ying Wang, 2014, Journal of Computer Science and Technology.

Parallel testing method for NoC using multicast path: Parallel testing method for NoC using multicast path

Xiaowei Li, Fang Fang, Yinhe Han, 2010 .

Embedded Test Resource to Reduce the Required Memory and Channels of Tester

Huawei Li, Xiaowei Li, Yinhe Han, 2005, 2005 IEEE Instrumentationand Measurement Technology Conference Proceedings.

An abacus turn model for time/space-efficient reconfigurable routing

Huawei Li, Xiaowei Li, Jun Ma, 2011, 2011 38th Annual International Symposium on Computer Architecture (ISCA).

Maximum power-up current estimation of power-gated circuits

Zuying Luo, Xiaowei Li, Yongjun Xu, 2003, ASICON 2003.

Theoretic analysis and enhanced x-tolerance of test response compact based on convolutional code

Huawei Li, Yinhe Han, Xiaowei Li, 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

BoDNoC: Providing bandwidth-on-demand interconnection for multi-granularity memory systems

Xiaowei Li, Yinhe Han, Ying Wang, 2017, 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC).

See and Think: Disentangling Semantic Scene Completion

Yu Hu, Yinhe Han, Yiming Zeng, 2018, NeurIPS.

DeepBurning: Automatic generation of FPGA-based learning accelerators for the Neural Network family

Jie Xu, Huawei Li, Xiaowei Li, 2016, 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC).

CPicker: Leveraging Performance-Equivalent Configurations to Improve Data Center Energy Efficiency

Xin He, Huawei Li, Yinhe Han, 2018, Journal of Computer Science and Technology.

PowerTrader: Enforcing Autonomous Power Management for Future Large-Scale Many-Core Processors

Yinhe Han, Xiaowei Li, Guihai Yan, 2017, IEEE Transactions on Multi-Scale Computing Systems.

ReviveNet: A Self-Adaptive Architecture for Improving Lifetime Reliability via Localized Timing Adaptation

Xiaowei Li, Yinhe Han, Guihai Yan, 2011, IEEE Transactions on Computers.

Amphisbaena: Modeling two orthogonal ways to hunt on heterogeneous many-cores

Xiaowei Li, Jun Ma, Yinhe Han, 2014, 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC).

FePIM: Contention-Free In-Memory Computing Based on Ferroelectric Field-Effect Transistors

Yinhe Han, Xiaoming Chen, Yuping Wu, 2021, 2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC).

Eliminating Iterations of Iterative Methods: Solving Large-Scale Sparse Linear System in O(1) with RRAM-based In-Memory Accelerator

Yinhe Han, Xiaoming Chen, Tao Song, 2021, ACM Great Lakes Symposium on VLSI.

Integrating Two Logics Into One Crossbar Array for Logic Gate Design

Peng Liu, Yinhe Han, Jigang Wu, 2021, IEEE Transactions on Circuits and Systems II: Express Briefs.

Breaking the von Neumann bottleneck: architecture-level processing-in-memory technology

Xingqi Zou, Yinhe Han, Xiaoming Chen, 2021, Science China Information Sciences.