Shirshendu Das

发表

Cost effective routing techniques in 2D mesh NoC using on-chip transmission lines

Dipika Deb, John Jose, Shirshendu Das, 2019, J. Parallel Distributed Comput..

A Framework for Block Placement, Migration, and Fast Searching in Tiled-DNUCA Architecture

Shirshendu Das, Hemangee K. Kapoor, 2016, TODE.

A reduced overhead replacement policy for Chip Multiprocessors having victim retention

Shirshendu Das, Hemangee K. Kapoor, Dhantu Buragohain, 2014, 2014 International Conference on Electronics and Communication Systems (ICECS).

Latency Aware Block Replacement for L1 Caches in Chip Multiprocessor

Shirshendu Das, Hemangee K. Kapoor, 2017, 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

Dynamic Thermal Management by Using Task Migration in Conjunction with Frequency Scaling for Chip Multiprocessors

Shirshendu Das, Hemangee K. Kapoor, Alankar V. Umdekar, 2018, 2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID).

State Preserving Dynamic DRAM Bank Re-Configurations for Enhanced Power Efficiency

Shirshendu Das, Dip Sankar Banerjee, Hemanta Kumar Mondal, 2019, 20th International Symposium on Quality Electronic Design (ISQED).

Towards a Better Cache Utilization Using Controlled Cache Partitioning

Shirshendu Das, Hemangee K. Kapoor, Prateek D. Halwe, 2013, 2013 IEEE 11th International Conference on Dependable, Autonomic and Secure Computing.

Dynamic associativity management using utility based way-sharing

Shirshendu Das, Hemangee K. Kapoor, 2015, SAC.

Performance Constrained Static Energy Reduction Using Way-Sharing Target-Banks

Shirshendu Das, Hemangee K. Kapoor, Shounak Chakraborty, 2015, 2015 IEEE International Parallel and Distributed Processing Symposium Workshop.

Towards a Better Cache Utilization by Selective Data Storage for CMP Last Level Caches

Shirshendu Das, Hemangee K. Kapoor, 2016, 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID).

Static energy reduction by performance linked cache capacity management in tiled CMPs

Shirshendu Das, Hemangee K. Kapoor, Shounak Chakraborty, 2015, SAC.

FORMAL MODELLING AND VERIFICATION OF COMPENSATING WEB TRANSACTIONS

Shirshendu Das, Hemangee K. Kapoor, Ka Lok Man, 2013 .

RT-DVS for Power Optimization in Multiprocessor Real-Time Systems

Shirshendu Das, Hemangee K. Kapoor, B. Venkateswarlu Naik, 2014, 2014 International Conference on Information Technology.

Dynamic Associativity Management Using Fellow Sets

Shirshendu Das, Hemangee K. Kapoor, 2013, 2013 International Symposium on Electronic System Design.

Effective Utilisation of LLCs by Managing Associativity, Placement and Mapping

Shirshendu Das, 2016 .

An Approach for Multicast Routing in Networks-on-Chip

Shirshendu Das, Hemangee K. Kapoor, M. Lakshmi Prasad, 2014, 2014 International Conference on Information Technology.

An efficient searching mechanism for dynamic NUCA in chip multiprocessors

Shirshendu Das, Hemangee K. Kapoor, Kartheek Vanapalli, 2015, 2015 19th International Symposium on VLSI Design and Test.

Dynamic associativity enabled DNUCA to improve block localisation in tiled CMPs

Shirshendu Das, Hemangee K. Kapoor, 2016, SAC.

A formal framework for interfacing mixed-timing systems

Shirshendu Das, Hemangee K. Kapoor, Parasara Sridhar Duggirala, 2013, Integr..

Power aware cache miss reduction by energy efficient victim retention

Shirshendu Das, Hemangee K. Kapoor, Shounak Chakraborty, 2015, 2015 19th International Symposium on VLSI Design and Test.

Dynamic Associativity Management in Tiled CMPs by Runtime Adaptation of Fellow Sets

Shirshendu Das, Hemangee K. Kapoor, 2017, IEEE Transactions on Parallel and Distributed Systems.

Victim retention for reducing cache misses in tiled chip multiprocessors

Shirshendu Das, Hemangee K. Kapoor, 2014, Microprocess. Microsystems.

CMP CACHE ARCHITECTURES - A SURVEY

Shirshendu Das, Shirshendu Das, 2013 .

Efficient Cache Resizing policy for DRAM-based LLCs in ChipMultiprocessors

Shirshendu Das, Nilkanta Sahu, Bindu Agarwalla, 2020 .

Tag only storage for capacity optimised last level cache in chip multiprocessors

Shirshendu Das, Hemangee K. Kapoor, Surajit Das, 2016, 2016 20th International Symposium on VLSI Design and Test (VDAT).

Random-LRU: A Replacement Policy for Chip Multiprocessors

Shirshendu Das, Hemangee K. Kapoor, Prateek D. Halwe, 2013, VDAT.

Static energy efficient cache reconfiguration for dynamic NUCA in tiled CMPs

Shirshendu Das, Hemangee K. Kapoor, Shounak Chakraborty, 2016, SAC.

Modelling and verification of compensating transactions using the SPIN tool

Shirshendu Das, Hemangee K. Kapoor, Ka Lok Man, 2012 .

Design and formal verification of a hierarchical cache coherence protocol for NoC based multiprocessors

Shirshendu Das, Hemangee K. Kapoor, Praveen Kanakala, 2012, The Journal of Supercomputing.

Exploration of Migration and Replacement Policies for Dynamic NUCA over Tiled CMPs

Shirshendu Das, Hemangee K. Kapoor, 2015, 2015 28th International Conference on VLSI Design.

Exploiting Secrets by Leveraging Dynamic Cache Partitioning of Last Level Cache

Shirshendu Das, Anurag Agarwal, Jaspinder Kaur, 2021, 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Towards Row Sensitive DRAM Refresh through Retention Awareness

Shirshendu Das, Dip Sankar Banerjee, Kaustav Goswami, 2021, 2021 22nd International Symposium on Quality Electronic Design (ISQED).

A Survey on Cache Timing Channel Attacks for Multicore Processors

Shirshendu Das, Jaspinder Kaur, Jaspinder Kaur, 2021, Journal of Hardware and Systems Security.

Towards Enhanced System Efficiency while Mitigating Row Hammer

Shirshendu Das, Dip Sankar Banerjee, Kaustav Goswami, 2021, ACM Trans. Archit. Code Optim..

A Fairness Conscious Cache Replacement Policy for Last Level Cache

Shirshendu Das, Kousik Kumar Dutta, Prathamesh Nitin Tanksale, 2021, 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE).