Hemangee K. Kapoor

发表

Cost effective routing techniques in 2D mesh NoC using on-chip transmission lines

Dipika Deb, John Jose, Shirshendu Das, 2019, J. Parallel Distributed Comput..

Static energy reduction by performance linked dynamic cache resizing

Hemangee K. Kapoor, Shounak Chakraborty, 2016, 2016 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC).

A Framework for Block Placement, Migration, and Fast Searching in Tiled-DNUCA Architecture

Shirshendu Das, Hemangee K. Kapoor, 2016, TODE.

Write-variation aware alternatives to replace SRAM buffers with non-volatile buffers in on-chip interconnects

Hemangee K. Kapoor, Khushboo Rani, H. Kapoor, 2019, IET Comput. Digit. Tech..

DidaSel: dirty data based selection of VC for effective utilization of NVM buffers in on-chip interconnects

Hemangee K. Kapoor, Khushboo Rani, Sukarn Agarwal, 2020, ISLPED.

Towards Controlling Chip Temperature by Dynamic Cache Reconfiguration in Multiprocessors

Hemangee K. Kapoor, Shounak Chakraborty, 2017, 2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID).

Reinforcement Learning Based Refresh Optimized Volatile STT-RAM Cache

Hemangee K. Kapoor, Shashank Suman, 2020, 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

Towards Analysing the Effect of Hybrid Caches on the Temperature of Tiled Chip Multi-Processors

Hemangee K. Kapoor, Khushboo Rani, Sukarn Agarwal, 2018, 2018 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS).

Modelling and analysis of wireless communication over Networks-on-Chip

Hemangee K. Kapoor, Apoorv Kumar, 2014, 18th International Symposium on VLSI Design and Test.

nZESPA: A Near-3D-Memory Zero Skipping Parallel Accelerator for CNNs

Hemangee K. Kapoor, Palash Das, 2020 .

A reduced overhead replacement policy for Chip Multiprocessors having victim retention

Shirshendu Das, Hemangee K. Kapoor, Dhantu Buragohain, 2014, 2014 International Conference on Electronics and Communication Systems (ICECS).

Fault Tolerance in Network on Chip Using Bypass Path Establishing Packets

Hemangee K. Kapoor, Sukarn Agarwal, Sharma Priya, 2018, 2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID).

Non-blocking Gated Buffers for Energy Efficient on-chip Interconnects in the era of Dark Silicon

Hemangee K. Kapoor, Khushboo Rani, Sukarn Agarwal, 2018, 2018 8th International Symposium on Embedded Computing and System Design (ISED).

Towards Analysing the Effect of Snoozy Caches on the Temperature of Tiled Chip Multi-Processors

Shrinivas P. Mahajan, Hemangee K. Kapoor, Khushboo Rani, 2018, 2018 8th International Symposium on Embedded Computing and System Design (ISED).

A Process Algebraic View of Latency-Insensitive Systems

Hemangee K. Kapoor, H. Kapoor, 2009, IEEE Transactions on Computers.

Latency Aware Block Replacement for L1 Caches in Chip Multiprocessor

Shirshendu Das, Hemangee K. Kapoor, 2017, 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

A Discrete Event System Approach to Online Testing of Speed Independent Circuits

Hemangee K. Kapoor, Santosh Biswas, Pradeep Kumar Biswal, 2015, VLSI Design.

Dynamic Thermal Management by Using Task Migration in Conjunction with Frequency Scaling for Chip Multiprocessors

Shirshendu Das, Hemangee K. Kapoor, Alankar V. Umdekar, 2018, 2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID).

Utility Aware Snoozy Caches for Energy Efficient Chip Multi-Processors

Shrinivas P. Mahajan, Hemangee K. Kapoor, Shounak Chakraborty, 2018, ACM Great Lakes Symposium on VLSI.

Performance linked dynamic cache tuning: A static energy reduction approach in tiled CMPs

Hemangee K. Kapoor, Shounak Chakraborty, 2017, Microprocess. Microsystems.

Controllable delay-insensitive processes and their reflection, interaction and factorisation

Hemangee K. Kapoor, Mark B. Josephs, M. B. Josephs, 2005, Fifth International Conference on Application of Concurrency to System Design (ACSD'05).

ZENCO: Zero-bytes based ENCOding for Non-Volatile Buffers in On-Chip Interconnects

Hemangee K. Kapoor, Khushboo Rani, 2020, 2020 57th ACM/IEEE Design Automation Conference (DAC).

Towards Optimizing Refresh Energy in embedded-DRAM Caches using Private Blocks

Hemangee K. Kapoor, Sukarn Agarwal, Sheel Sindhu Manohar, 2019, ACM Great Lakes Symposium on VLSI.

Towards a dynamic associativity enabled write prediction based hybrid cache

Hemangee K. Kapoor, Sukarn Agarwal, 2016, 2016 20th International Symposium on VLSI Design and Test (VDAT).

Decomposing specifications with concurrent outputs to resolve state coding conflicts in asynchronous logic synthesis

Hemangee K. Kapoor, Mark B. Josephs, M. B. Josephs, 2004, Proceedings. 41st Design Automation Conference, 2004..

Energy aware frame based fair scheduling

Hemangee K. Kapoor, Arnab Sarkar, Sanjay Moulik, 2018, Sustain. Comput. Informatics Syst..

Towards a Better Cache Utilization Using Controlled Cache Partitioning

Shirshendu Das, Hemangee K. Kapoor, Prateek D. Halwe, 2013, 2013 IEEE 11th International Conference on Dependable, Autonomic and Secure Computing.

Towards Near Data Processing of Convolutional Neural Networks

Hemangee K. Kapoor, Palash Das, Shivam Lakhotia, 2018, 2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID).

Dynamic associativity management using utility based way-sharing

Shirshendu Das, Hemangee K. Kapoor, 2015, SAC.

Refresh optimised embedded-dram caches based on zero data detection

Hemangee K. Kapoor, Sheel Sindhu Manohar, 2019, SAC.

Performance Constrained Static Energy Reduction Using Way-Sharing Target-Banks

Shirshendu Das, Hemangee K. Kapoor, Shounak Chakraborty, 2015, 2015 IEEE International Parallel and Distributed Processing Symposium Workshop.

Towards a Better Lifetime for Non-volatile Caches in Chip Multiprocessors

Hemangee K. Kapoor, Sukarn Agarwal, 2017, 2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID).

Verification and implementation of delay-insensitive processes in restrictive environments

Hemangee K. Kapoor, Mark B. Josephs, M. B. Josephs, 2004, Proceedings. Fourth International Conference on Application of Concurrency to System Design, 2004. ACSD 2004..

Cache capacity and its effects on power consumption for tiled chip multi-processors

Dipika Deb, Hemangee K. Kapoor, Shounak Chakraborty, 2014, 2014 International Conference on Electronics and Communication Systems (ICECS).

Towards a Better Cache Utilization by Selective Data Storage for CMP Last Level Caches

Shirshendu Das, Hemangee K. Kapoor, 2016, 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID).

Delay-Insensitive Processes: A Formal Approach to the Design of Asynchronous Circuits

Hemangee K. Kapoor, H. Kapoor, 2004 .

Multiprocessor revolution and cache management

Hemangee K. Kapoor, 2012 .

Fair diagnosability in PN-based DES models

Hemangee K. Kapoor, Santosh Biswas, Jatindra Kumar Deka, 2010, IEEE ICCA 2010.

Static energy reduction by performance linked cache capacity management in tiled CMPs

Shirshendu Das, Hemangee K. Kapoor, Shounak Chakraborty, 2015, SAC.

Lifetime Enhancement of Non-Volatile Caches by Exploiting Dynamic Associativity Management Techniques

Hemangee K. Kapoor, Sukarn Agarwal, 2017, VLSI-SoC.

Improving the Lifetime of Non-Volatile Cache by Write Restriction

Hemangee K. Kapoor, Sukarn Agarwal, 2019, IEEE Transactions on Computers.

FORMAL MODELLING AND VERIFICATION OF COMPENSATING WEB TRANSACTIONS

Shirshendu Das, Hemangee K. Kapoor, Ka Lok Man, 2013 .

Applying the Concurrency Workbench to the Verification of DI Circuits

Hemangee K. Kapoor, Mark B. Josephs, 2003 .

RT-DVS for Power Optimization in Multiprocessor Real-Time Systems

Shirshendu Das, Hemangee K. Kapoor, B. Venkateswarlu Naik, 2014, 2014 International Conference on Information Technology.

Dynamic Associativity Management Using Fellow Sets

Shirshendu Das, Hemangee K. Kapoor, 2013, 2013 International Symposium on Electronic System Design.

LiNoVo: Longevity Enhancement of Non-Volatile Last Level Caches in Chip Multiprocessors

Hemangee K. Kapoor, Sukarn Agarwal, 2020, 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

Targeting inter set write variation to improve the lifetime of non-volatile cache using fellow sets

Hemangee K. Kapoor, Sukarn Agarwal, 2017, 2017 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC).

Reuse Distance-based Victim Cache for Effective Utilisation of Hybrid Main Memory System

Hemangee K. Kapoor, Sukarn Agarwal, Arijit Nath, 2020, ACM Trans. Design Autom. Electr. Syst..

Write Variation Aware Non-volatile Buffers for On-Chip Interconnects

Hemangee K. Kapoor, Khushboo Rani, 2019, 2019 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID).

Formal Modelling and Verification of an Asynchronous DLX Pipeline

Hemangee K. Kapoor, H. Kapoor, 2006, Fourth IEEE International Conference on Software Engineering and Formal Methods (SEFM'06).

TARTS: A Temperature-Aware Real-Time Deadline-Partitioned Fair Scheduler

Hemangee K. Kapoor, Arnab Sarkar, Sanjay Moulik, 2020, J. Syst. Archit..

Towards Near-Data Processing of Compare Operations in 3D-Stacked Memory

Hemangee K. Kapoor, Palash Das, 2018, ACM Great Lakes Symposium on VLSI.

An Approach for Multicast Routing in Networks-on-Chip

Shirshendu Das, Hemangee K. Kapoor, M. Lakshmi Prasad, 2014, 2014 International Conference on Information Technology.

Restricting writes for energy-efficient hybrid cache in multi-core architectures

Hemangee K. Kapoor, Sukarn Agarwal, 2016, 2016 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC).

Modelling Latency-Insensitive Systems in CSP

Hemangee K. Kapoor, H. Kapoor, 2007, Seventh International Conference on Application of Concurrency to System Design (ACSD 2007).

An efficient searching mechanism for dynamic NUCA in chip multiprocessors

Shirshendu Das, Hemangee K. Kapoor, Kartheek Vanapalli, 2015, 2015 19th International Symposium on VLSI Design and Test.

Dynamic associativity enabled DNUCA to improve block localisation in tiled CMPs

Shirshendu Das, Hemangee K. Kapoor, 2016, SAC.

A formal framework for interfacing mixed-timing systems

Shirshendu Das, Hemangee K. Kapoor, Parasara Sridhar Duggirala, 2013, Integr..

A Security Framework for NoC Using Authenticated Encryption and Session Keys

Hemangee K. Kapoor, Gaurav Trivedi, G. Bhoopal Rao, 2013, Circuits Syst. Signal Process..

Controllable Delay-Insensitive Processes

Hemangee K. Kapoor, Mark B. Josephs, M. B. Josephs, 2007, Fundam. Informaticae.

Power aware cache miss reduction by energy efficient victim retention

Shirshendu Das, Hemangee K. Kapoor, Shounak Chakraborty, 2015, 2015 19th International Symposium on VLSI Design and Test.

Dynamic Associativity Management in Tiled CMPs by Runtime Adaptation of Fellow Sets

Shirshendu Das, Hemangee K. Kapoor, 2017, IEEE Transactions on Parallel and Distributed Systems.

Write Variation Aware Buffer Assignment for Improved Lifetime of Non-Volatile Buffers in On-Chip Interconnects

Hemangee K. Kapoor, Khushboo Rani, 2019, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Exploring Use of NoC for Reconfigurable Video Coding

Hemangee K. Kapoor, Alpesh Patel, 2010, 2010 23rd International Conference on VLSI Design.

Victim retention for reducing cache misses in tiled chip multiprocessors

Shirshendu Das, Hemangee K. Kapoor, 2014, Microprocess. Microsystems.

Lightweight Message Encoding of Power-Gating Controller for On-Time Wakeup of Gated Router in Network-on-Chip

Hemangee K. Kapoor, Neelkamal, Sonal Yadav, 2019, 2019 9th International Symposium on Embedded Computing and System Design (ISED).

Tag only storage for capacity optimised last level cache in chip multiprocessors

Shirshendu Das, Hemangee K. Kapoor, Surajit Das, 2016, 2016 20th International Symposium on VLSI Design and Test (VDAT).

Modelling and Veriflcation of Delay-Insensitive Circuits using CCS and the

Hemangee K. Kapoor, Mark B. Josephs, Concurrency Workbench, 2003 .

A New Recursive Partitioning Multicast Routing Algorithm for 3D Network-on-Chip

Hemangee K. Kapoor, Shounak Chakraborty, Narendra Kumar Meena, 2014, 18th International Symposium on VLSI Design and Test.

Highly Resilient Minimal Path Routing Algorithm for Fault Tolerant Network-on-Chips

Hemangee K. Kapoor, Chi-Un Lei, Ka Lok Man, 2011 .

Exploring the Role of Large Centralised Caches in Thermal Efficient Chip Design

Hemangee K. Kapoor, Shounak Chakraborty, Shounak Chakraborty, 2019, ACM Trans. Design Autom. Electr. Syst..

Modelling and verification of delay-insensitive circuits using CCS and the Concurrency Workbench

Hemangee K. Kapoor, Mark B. Josephs, M. B. Josephs, 2004, Inf. Process. Lett..

Formal Verification and Synthesis Of Null Conventional Logic Circuits

Hemangee K. Kapoor, Chi-Un Lei, Ka Lok Man, 2012, IMECS 2012.

DPFair Scheduling with Slowdown and Suspension

Hemangee K. Kapoor, Arnab Sarkar, Sanjay Moulik, 2018, 2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID).

Enhancing the Lifetime of Non-Volatile Caches by Exploiting Module-Wise Write Restriction

Hemangee K. Kapoor, Sukarn Agarwal, 2019, ACM Great Lakes Symposium on VLSI.

A Power Efficient Crossbar Arbitration in Multi-NoC for Multicast and Broadcast Traffic

Manoj Singh Gaur, Mark Zwolinski, Hemangee K. Kapoor, 2018, 2018 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS).

Random-LRU: A Replacement Policy for Chip Multiprocessors

Shirshendu Das, Hemangee K. Kapoor, Prateek D. Halwe, 2013, VDAT.

Static energy efficient cache reconfiguration for dynamic NUCA in tiled CMPs

Shirshendu Das, Hemangee K. Kapoor, Shounak Chakraborty, 2016, SAC.

An Authenticated Encryption Based Security Framework for NoC Architectures

Hemangee K. Kapoor, K. Sajeesh, H. Kapoor, 2011, 2011 International Symposium on Electronic System Design.

Formal Approach for DVS-Based Power Management for Multiple Server System in Presence of Server Failure and Repair

Hemangee K. Kapoor, Lalit Chandnani, 2013, IEEE Transactions on Industrial Informatics.

Modelling and verification of compensating transactions using the SPIN tool

Shirshendu Das, Hemangee K. Kapoor, Ka Lok Man, 2012 .

PAFSV: A Formal Framework for Specification and Analysis of SystemVerilog

Hemangee K. Kapoor, Nan Zhang, Chi-Un Lei, 2016, Comput. Informatics.

Write Variation Aware Cache Partitioning for Improved Lifetime in Non-volatile Caches

Hemangee K. Kapoor, Arijit Nath, 2019, 2019 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID).

WELCOMF: wear leveling assisted compression using frequent words in non-volatile main memories

Hemangee K. Kapoor, Arijit Nath, 2020, ISLPED.

Analysing the Role of Last Level Caches in Controlling Chip Temperature

Hemangee K. Kapoor, Shounak Chakraborty, Shounak Chakraborty, 2018, IEEE Transactions on Sustainable Computing.

Design and formal verification of a hierarchical cache coherence protocol for NoC based multiprocessors

Shirshendu Das, Hemangee K. Kapoor, Praveen Kanakala, 2012, The Journal of Supercomputing.

Late Breaking Results: Improving Static Power Efficiency via Placement of Network Demultiplexer over Control Plane of Router in Multi-NoCs

Vijay Laxmi, Manoj Singh Gaur, Hemangee K. Kapoor, 2019, 2019 56th ACM/IEEE Design Automation Conference (DAC).

Reuse-Distance-Aware Write-Intensity Prediction of Dataless Entries for Energy-Efficient Hybrid Caches

Hemangee K. Kapoor, Sukarn Agarwal, 2018, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Dimming Hybrid Caches to Assist in Temperature Control of Chip MultiProcessors

Hemangee K. Kapoor, Palash Das, Chirag Joshi, 2020, ACM Great Lakes Symposium on VLSI.

Dynamic reconfiguration of embedded-DRAM caches employing zero data detection based refresh optimisation

Hemangee K. Kapoor, Sheel Sindhu Manohar, 2019, J. Syst. Archit..

Exploration of Migration and Replacement Policies for Dynamic NUCA over Tiled CMPs

Shirshendu Das, Hemangee K. Kapoor, 2015, 2015 28th International Conference on VLSI Design.

A Soft Real-time Memory Request Scheduler for Phase Change Memory Systems

Hemangee K. Kapoor, N. S. Aswathy, Arnab Sarkar, 2021, 2021 IEEE 27th International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA).

DAMUS: Dynamic Allocation based on Write Frequency in MUlti-Retention STT-RAM based Last Level Caches

Hemangee K. Kapoor, Mayank Baranwal, Sukarn Agarwal, 2021, 2021 22nd International Symposium on Quality Electronic Design (ISQED).

SeNonDiv: Securing Non-Volatile Memory using Hybrid Memory and Critical Data Diversion

Hemangee K. Kapoor, Arijit Nath, Manik B. Bhosle, 2021, 2021 22nd International Symposium on Quality Electronic Design (ISQED).

Investigating Frequency Scaling, Nonvolatile, and Hybrid Memory Technologies for On-Chip Routers to Support the Era of Dark Silicon

Hemangee K. Kapoor, Khushboo Rani, 2021, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.