Victor Bandur

Unifying Theories of Logic and Specification

Jim Woodcock, Victor Bandur, J. Woodcock, 2013, SBMF.

Unifying theories of logics with undefinedness

Victor Bandur, V. Bandur, 2014 .

Unifying Theories of Undefinedness in UTP

Jim Woodcock, Victor Bandur, J. Woodcock, 2012, UTP.

Informing Assurance Case Review Through a Formal Interpretation of GSN Core Logic

John McDermid, Victor Bandur, 2015, SAFECOMP Workshops.

Microcontroller Assembly Synthesis from Timed Automaton Task Specifications

Alan Wassyng, Wolfram Kahl, Victor Bandur, 2012, FMICS.

Hard Real-Time Microcontroller Code Generation from Timed Automaton Specifications

B. Eng, Victor Bandur, B. Eng, 2008 .

Code generation for distributed embedded systems with VDM-RT

Peter Gorm Larsen, Julien Ouy, Tommaso Fabbri, 2019, Design Automation for Embedded Systems.

Something is Rotten in the State of Documenting Simulink Models

Alan Wassyng, Mark Lawford, Vera Pantelic, 2019, MODELSWARD.