H. Ohno

发表

A 600MHz MTJ-based nonvolatile latch making use of incubation time in MTJ switching

T. Endoh, S. Togashi, F. Iga, 2011, 2011 International Electron Devices Meeting.

A 1.5nsec/2.1nsec random read/write cycle 1Mb STT-RAM using 6T2MTJ cell with background write for nonvolatile e-memories

T. Endoh, T. Ohsawa, S. Ikeda, 2013, 2013 Symposium on VLSI Circuits.

Ultrafast parallel reconfiguration of 3D-stacked reconfigurable spin logic chip with on-chip SPRAM (SPin-transfer torque RAM)

H. Ohno, M. Koyanagi, K. Kiyoyama, 2012, 2012 Symposium on VLSI Technology (VLSIT).

32-Mb 2T1R SPRAM with localized bi-directional write driver and ‘1’/‘0’ dual-array equalized reference cell

S. Ikeda, H. Ohno, T. Kawahara, 2009, 2009 Symposium on VLSI Circuits.

TMR Design Methodology for SPin-Transfer Torque RAM (SPRAM) with Nonvolatile and SRAM Compatible Operations

S. Ikeda, H. Ohno, T. Kawahara, 2008, 2008 Joint Non-Volatile Semiconductor Memory Workshop and International Conference on Memory Technology and Design.

2Mb SPRAM Design: Bi-Directional Current Write and Parallelizing-Direction Current Read Schemes Based on Spin-Transfer Torque Switching

S. Ikeda, H. Ohno, H. Matsuoka, 2007, 2007 IEEE International Conference on Integrated Circuit Design and Technology.

Design of LCD for Electronic Instrument Cluster

H. Ohno, H. Tanaka, K. Toriyama, 1985 .

Restructuring of memory hierarchy in computing system with spintronics-based technologies

T. Endoh, T. Ohsawa, H. Koike, 2012, 2012 Symposium on VLSI Technology (VLSIT).

Highly-scalable disruptive reading scheme for Gb-scale SPRAM and beyond

H. Ohno, T. Kawahara, K. Ono, 2010, 2010 IEEE International Memory Workshop.

Fabrication of a 99%-energy-less nonvolatile multi-functional CAM chip using hierarchical power gating for a massively-parallel full-text-search engine

T. Endoh, S. Fukami, S. Ikeda, 2013, 2013 Symposium on VLSI Technology.

A 500ps/8.5ns Array Read/Write Latency 1Mb Twin 1T1MTJ STT-MRAM designed in 90nm CMOS/40nm MTJ Process with Novel Positive Feedback S/A Circuit

Tetsuo Endoh, Takahiro Hanyu, H. Ohno, 2014 .

A Power-gated 32bit MPU with a Power Controller Circuit Activated by Deep-sleep-mode Instruction Achieving Ultra-low Power Operation

Tetsuo Endoh, Takahiro Hanyu, H. Ohno, 2014 .

Design of a variation-resilient single-ended non-volatile six-input lookup table circuit with a redundant-magnetic tunnel junction-based active load for smart Internet-of-things applications

Tetsuo Endoh, Takahiro Hanyu, H. Ohno, 2017 .

A hybrid CMOS/magnetic tunnel junction approach for nonvolatile integrated circuits

H. Ohno, 2006, 2009 Symposium on VLSI Technology.

A novel SPRAM (SPin-transfer torque RAM)-based reconfigurable logic block for 3D-stacked reconfigurable spin processor

S. Ikeda, H. Ohno, M. Koyanagi, 2008, 2008 IEEE International Electron Devices Meeting.

A multi-level-cell spin-transfer torque memory with series-stacked magnetotunnel junctions

H. Ohno, T. Kawahara, K. Ono, 2010, 2010 Symposium on VLSI Technology.

A content addressable memory using magnetic domain wall motion cells

T. Endoh, S. Fukami, N. Kasai, 2011, 2011 Symposium on VLSI Circuits - Digest of Technical Papers.

A power-gated MPU with 3-microsecond entry/exit delay using MTJ-based nonvolatile flip-flop

T. Endoh, T. Ohsawa, H. Koike, 2013, 2013 IEEE Asian Solid-State Circuits Conference (A-SSCC).

Three-terminal spintronics memory devices with perpendicular anisotropy

S. Fukami, H. Ohno, 2015, 2015 IEEE Magnetics Conference (INTERMAG).

SPRAM (SPin-transfer torque RAM) Technology for Green IT World

H. Ohno, T. Kawahara, H. Takahashi, 2008, 2008 IEEE International Conference on Electron Devices and Solid-State Circuits.

Proposal and demonstration of a new spin-orbit torque induced switching device

S. Fukami, H. Ohno, T. Anekawa, 2015, 2015 IEEE Magnetics Conference (INTERMAG).

Spintronics primitive gate with high error correction efficiency 6(Perror)2 for logic-in memory architecture

T. Endoh, S. Fukami, N. Kasai, 2012, 2012 Symposium on VLSI Technology (VLSIT).

20-nm magnetic domain wall motion memory with ultralow-power operation

S. Fukami, S. Ikeda, N. Kasai, 2013, 2013 IEEE International Electron Devices Meeting.

Spin transport and spin torque in antiferromagnetic devices

H. Ohno, K. Olejník, H. Ohno, 2018 .

Perpendicular Magnetic Tunnel Junctions with CoFe/Pd Multilayer Electrodes and an MgO Barrier

H. Ohno, K. Miura, F. Matsukura, 2009, IEEE Transactions on Magnetics.

Current-Induced Magnetization Switching in MgO Barrier Magnetic Tunnel Junctions With CoFeB-Based Synthetic Ferrimagnetic Free Layers

H. Ohno, T. Kawahara, R. Takemura, 2008, IEEE Transactions on Magnetics.

High-speed and reliable domain wall motion device: Material design for embedded memory and logic application

S. Fukami, S. Ikeda, N. Kasai, 2012, 2012 Symposium on VLSI Technology (VLSIT).

A novel SPRAM (SPin-transfer torque RAM) with a synthetic ferrimagnetic free layer for higher immunity to read disturbance and reducing write-current dispersion

H. Ohno, T. Kawahara, R. Takemura, 2007, 2007 IEEE Symposium on VLSI Technology.

CoFeB/MgO based perpendicular magnetic tunnel junctions with stepped structure for symmetrizing different retention times of “0” and “1” information

S. Ikeda, H. Ohno, K. Miura, 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

Scalability Prospect of Three-Terminal Magnetic Domain-Wall Motion Device

S. Fukami, S. Ikeda, N. Kasai, 2012, IEEE Transactions on Magnetics.

CoFeB Thickness Dependence of Thermal Stability Factor in CoFeB/MgO Perpendicular Magnetic Tunnel Junctions

S. Ikeda, H. Ohno, K. Miura, 2012, IEEE Magnetics Letters.

SPRAM with large thermal stability for high immunity to read disturbance and long retention for high-temperature operation

S. Ikeda, H. Ohno, T. Kawahara, 2006, 2009 Symposium on VLSI Technology.

First demonstration of field-free SOT-MRAM with 0.35 ns write speed and 70 thermal stability under 400°C thermal tolerance by canted SOT structure and its advanced patterning/SOT channel technology

T. Endoh, S. Fukami, S. Ikeda, 2019, 2019 IEEE International Electron Devices Meeting (IEDM).

Current-induced domain-wall switching in a ferromagnetic semiconductor structure

H. Ohno, F. Matsukura, M. Yamanouchi, 2004, Nature.

Hole-mediated ferromagnetism in tetrahedrally coordinated semiconductors

H. Ohno, F. Matsukura, H. Ohno, 2000, cond-mat/0007190.

Low-current domain wall motion MRAM with perpendicularly magnetized CoFeB/MgO magnetic tunnel junction and underlying hard magnets

S. Fukami, S. Ikeda, H. Ohno, 2013, 2013 Symposium on VLSI Technology.

Magnetoresistive Random Access Memory with Spin Transfer Torque Write (Spin RAM) - Present and Future -

H. Ohno, 2011 .

A 1.5nsec/2.1nsec random read/write cycle 1Mb STT-RAM using 6T2MTJ cell with background write for nonvolatile e-memories

T. Ohsawa, T. Endoh, S. Ikeda, 2013, 2013 Symposium on VLSI Technology.

MgO barrier-perpendicular magnetic tunnel junctions with CoFe/Pd multilayers and ferromagnetic insertion layers

S. Ikeda, H. Ohno, K. Miura, 2009, 0910.4204.

Semiconductor spintronics

H. Ohno, H. Ohno, H. Akinaga, 2002 .

Studies on Static Noise Margin and Scalability for Low-Power and High-Density Nonvolatile SRAM using Spin-Transfer-Torque (STT) MTJs

Tetsuo Endoh, Takahiro Hanyu, F. Iga, 2011 .

Modeling and simulation of polycrystalline ZnO thin-film transistors

H. Ohno, S. Takagi, Tokyo Institute of Technology, 2003 .